For my bachelor thesis I have to analyse the effecs of False Sharing on multicore systems. So looking for the different cache-coherence-protocol-types I have come across on Wikipedia that Intel has developed the MESIF cache-coherence-protocol, but there is no information that Intel also uses this.
Looking at the manual Intel® 64 and IA-32 Architectures Developer's Manual: Vol. 3A I couldn't find anything about MESIF but the MESI-protocol. So the question is, doesn't Intel use its own cache-coherence-protocol. Or am I searching it in the wrong document.
Intel uses MESIF protocol (http://www.realworldtech.com/common-system-interface/5/, https://en.wikipedia.org/wiki/MESIF_protocol) in QuickPath and AMD uses MOESI protocol (https://en.wikipedia.org/wiki/MOESI_protocol, http://www.m5sim.org/MOESI_hammer) with or without Probe Filter in HyperTransport. But these protocols are for inter-chip communication (a AMD bulldozer socket has 2 chips in MCM). As far as I know, in both processors intra-chip coherence is made at L3 cache.
A tool you could use to check for NUMA performance issues is numagrind: http://dx.doi.org/10.1109/IPDPS.2011.100