I am trying to use MIG 7 to interface a DDR3 ram to an Artix 7 FPGA. I am very new in using IP and I only know VHDL (not Verilog). I have uploaded my code. In my code the init_calib_complete never goes high !
Anybody can find what is wrong with my code or give me a sample code, please.
-I only use the last few lines for my codes, the rest of that are just declaration.
-I have connected LEDV7 and LEDV6 to LEDs.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
entity Main_PRG is
Port (
-- Inouts
ddr3_dq : inout std_logic_vector(7 downto 0);
ddr3_dqs_p : inout std_logic_vector(0 downto 0);
ddr3_dqs_n : inout std_logic_vector(0 downto 0);
-- Outputs
ddr3_addr : out std_logic_vector(13 downto 0);
ddr3_ba : out std_logic_vector(2 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_ck_p : out std_logic_vector(0 downto 0);
ddr3_ck_n : out std_logic_vector(0 downto 0);
ddr3_cke : out std_logic_vector(0 downto 0);
ddr3_cs_n : out std_logic_vector(0 downto 0);
ddr3_odt : out std_logic_vector(0 downto 0);
-- Inputs
-- Differential system clocks
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
-- Single-ended iodelayctrl clk (reference clock)
clk_ref_i : in std_logic;
LEDV6 : out STD_LOGIC ;
LEDV7 : out STD_LOGIC
);
end Main_PRG;
architecture Behavioral of Main_PRG is
signal app_addr : std_logic_vector(27 downto 0);
signal app_addr : std_logic_vector(27 downto 0);
signal app_addr_i : std_logic_vector(31 downto 0);
signal app_cmd : std_logic_vector(2 downto 0);
signal app_en : std_logic;
signal app_rdy : std_logic;
signal app_rdy_i : std_logic;
signal app_rd_data : std_logic_vector(63 downto 0);
signal app_rd_data_end : std_logic;
signal app_rd_data_valid : std_logic;
signal app_rd_data_valid_i : std_logic;
signal app_wdf_data : std_logic_vector(63 downto 0);
signal app_wdf_end : std_logic;
signal app_wdf_rdy : std_logic;
signal app_wdf_rdy_i : std_logic;
signal app_sr_active : std_logic;
signal app_ref_ack : std_logic;
signal app_zq_ack : std_logic;
signal app_wdf_wren : std_logic;
signal mem_pattern_init_done : std_logic_vector(0 downto 0);
signal modify_enable_sel : std_logic;
signal data_mode_manual_sel : std_logic_vector(2 downto 0);
signal addr_mode_manual_sel : std_logic_vector(2 downto 0);
signal cmp_error : std_logic;
signal tg_wr_data_counts : std_logic_vector(47 downto 0);
signal tg_rd_data_counts : std_logic_vector(47 downto 0);
signal init_calib_complete_i : std_logic;
signal tg_compare_error_i : std_logic;
signal tg_rst : std_logic;
signal po_win_tg_rst : std_logic;
signal manual_clear_error : std_logic_vector(0 downto 0);
signal clk : std_logic;
signal rst : std_logic;
signal vio_modify_enable : std_logic_vector(0 downto 0);
signal vio_data_mode_value : std_logic_vector(3 downto 0);
signal vio_pause_traffic : std_logic_vector(0 downto 0);
signal vio_addr_mode_value : std_logic_vector(2 downto 0);
signal vio_instr_mode_value : std_logic_vector(3 downto 0);
signal vio_bl_mode_value : std_logic_vector(1 downto 0);
signal vio_fixed_instr_value : std_logic_vector(2 downto 0);
signal vio_data_mask_gen : std_logic_vector(0 downto 0);
signal dbg_clear_error : std_logic_vector(0 downto 0);
signal vio_tg_rst : std_logic_vector(0 downto 0);
signal dbg_sel_pi_incdec : std_logic_vector(0 downto 0);
signal dbg_pi_f_inc : std_logic_vector(0 downto 0);
signal dbg_pi_f_dec : std_logic_vector(0 downto 0);
signal dbg_sel_po_incdec : std_logic_vector(0 downto 0);
signal dbg_po_f_inc : std_logic_vector(0 downto 0);
signal dbg_po_f_stg23_sel : std_logic_vector(0 downto 0);
signal dbg_po_f_dec : std_logic_vector(0 downto 0);
signal vio_dbg_sel_pi_incdec : std_logic_vector(0 downto 0);
signal vio_dbg_pi_f_inc : std_logic_vector(0 downto 0);
signal vio_dbg_pi_f_dec : std_logic_vector(0 downto 0);
signal vio_dbg_sel_po_incdec : std_logic_vector(0 downto 0);
signal vio_dbg_po_f_inc : std_logic_vector(0 downto 0);
signal vio_dbg_po_f_stg23_sel : std_logic_vector(0 downto 0);
signal vio_dbg_po_f_dec : std_logic_vector(0 downto 0);
signal all_zeros1 : std_logic_vector(31 downto 0):= (others => '0');
signal all_zeros2 : std_logic_vector(38 downto 0):= (others => '0');
signal wdt_en_w : std_logic_vector(0 downto 0);
signal cmd_wdt_err_w : std_logic;
signal wr_wdt_err_w : std_logic;
signal rd_wdt_err_w : std_logic;
signal cntr2 : std_logic_vector(31 downto 0):= (others => '0');
signal cntr1 : std_logic_vector(31 downto 0):= (others => '0');
component DDR3_RAM
port(
ddr3_dq : inout std_logic_vector(7 downto 0);
ddr3_dqs_p : inout std_logic_vector(0 downto 0);
ddr3_dqs_n : inout std_logic_vector(0 downto 0);
ddr3_addr : out std_logic_vector(13 downto 0);
ddr3_ba : out std_logic_vector(2 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_ck_p : out std_logic_vector(0 downto 0);
ddr3_ck_n : out std_logic_vector(0 downto 0);
ddr3_cke : out std_logic_vector(0 downto 0);
ddr3_cs_n : out std_logic_vector(0 downto 0);
ddr3_odt : out std_logic_vector(0 downto 0);
app_addr : in std_logic_vector(27 downto 0);
app_cmd : in std_logic_vector(2 downto 0);
app_en : in std_logic;
app_wdf_data : in std_logic_vector(63 downto 0);
app_wdf_end : in std_logic;
app_wdf_wren : in std_logic;
app_rd_data : out std_logic_vector(63 downto 0);
app_rd_data_end : out std_logic;
app_rd_data_valid : out std_logic;
app_rdy : out std_logic;
app_wdf_rdy : out std_logic;
app_sr_req : in std_logic;
app_ref_req : in std_logic;
app_zq_req : in std_logic;
app_sr_active : out std_logic;
app_ref_ack : out std_logic;
app_zq_ack : out std_logic;
ui_clk : out std_logic;
ui_clk_sync_rst : out std_logic;
init_calib_complete : out std_logic;
-- System Clock Ports
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
-- Reference Clock Ports
clk_ref_i : in std_logic;
sys_rst : in std_logic
);
end component DDR3_RAM;
----------------------------------------------------------
---DDR RAM Interface signals
----------------------------------------------------------
CONSTANT READ_CMD : STD_LOGIC_VECTOR (2 downto 0) := "001";
CONSTANT WRITE_CMD : STD_LOGIC_VECTOR (2 downto 0) := "000";
signal data_1 : std_logic_vector (63 downto 0);
signal data_2 : std_logic_vector (63 downto 0);
type state_machine is (Init, Write_1, Set_Data_1, Write_2, Set_Data_2,
Read_Prep_1, Read_1, Read_Wait_1, Read_Prep_2, Read_2, Read_Wait_2,
Done);
signal state : state_machine := Init;
signal next_state : state_machine;
signal Curr_State : std_logic_vector(2 downto 0):="000";
signal Reset : std_logic := '0' ;
begin
u_DDR3_RAM : DDR3_RAM
port map (
-- Memory interface ports
ddr3_addr => ddr3_addr,
ddr3_ba => ddr3_ba,
ddr3_cas_n => ddr3_cas_n,
ddr3_ck_n => ddr3_ck_n,
ddr3_ck_p => ddr3_ck_p,
ddr3_cke => ddr3_cke,
ddr3_ras_n => ddr3_ras_n,
ddr3_reset_n => ddr3_reset_n,
ddr3_we_n => ddr3_we_n,
ddr3_dq => ddr3_dq,
ddr3_dqs_n => ddr3_dqs_n,
ddr3_dqs_p => ddr3_dqs_p,
init_calib_complete => init_calib_complete_i,
ddr3_cs_n => ddr3_cs_n,
ddr3_odt => ddr3_odt,
-- Application interface ports
app_addr => app_addr,
app_cmd => app_cmd,
app_en => app_en,
app_wdf_data => app_wdf_data,
app_wdf_end => app_wdf_end,
app_wdf_wren => app_wdf_wren,
app_rd_data => app_rd_data,
app_rd_data_end => app_rd_data_end,
app_rd_data_valid => app_rd_data_valid,
app_rdy => app_rdy,
app_wdf_rdy => app_wdf_rdy,
app_sr_req => '0',
app_ref_req => '0',
app_zq_req => '0',
app_sr_active => app_sr_active,
app_ref_ack => app_ref_ack,
app_zq_ack => app_zq_ack,
ui_clk => clk,
ui_clk_sync_rst => rst,
-- System Clock Ports
sys_clk_p => sys_clk_p,
sys_clk_n => sys_clk_n,
-- Reference Clock Ports
clk_ref_i => clk_ref_i,
sys_rst => '1'
);
-- End of User Design top instance
process(clk)
begin
if rising_edge(clk) then
if cntr1(27) = '0' then
cntr1 <= cntr1 + 1 ;
end if;
end if ;
end process ;
Reset <= cntr1(28) ;
process (clk)
begin
if rising_edge(clk) then
if init_calib_complete_i = '1' then
LEDV6 <= '1' ;
LEDV7 <= '0' ;
else
LEDV6 <= '1' ;
LEDV7 <= '1' ;
end if;
if Reset = '0' then
app_en <= '0';
app_wdf_wren <= '0';
app_wdf_end <= '0';
app_cmd <= (others => '0');
app_addr <= (others => '0');
app_wdf_data <= (others => '0');
state <= Init;
else
app_en <= '0';
app_wdf_wren <= '0';
app_wdf_end <= '0';
app_cmd <= (others => '0');
app_addr <= (others => '0');
app_wdf_data <= (others => '0');
--LEDV6 <= '1' ;
--LEDV7 <= '1' ;
case state is
when Init =>
Curr_State <= "001";
data_1 <= (others => '0');
data_2 <= (others => '0');
--LEDV6 <= '1' ;
--LEDV7 <= '0' ;
if app_rdy = '1' then
state <= Write_1;
else
state <= Init;
end if;
when Write_1 =>
--LEDV6 <= '0' ;
--LEDV7 <= '0' ;
when others =>
--LEDV6 <= '0' ;
--LEDV6 <= '0' ;
end case;
end if ;
end if;
end process;
end Behavioral;
Thanks every body I found I have problem with clock. Since ui_clk_sync_rst signal was always low, I guessed it must be clock problem. In my design, I have a 27 MHz and a 25 MHz input clocks. MIG-7, Does not let the user assign generated clock with internal PLL as reference and system clocks due to jitter problem. For external clock the minimum input clock has to be 50MHz. But there is a solution. The solution is to change the generated IP. Thanks everyone.