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vhdlxilinxxilinx-isespartan

VHDL <b_Off_OBUF> is incomplete. The signal is not driven by any source pin in the design

I'm trying to write a very simple program on a Spartan-3E development board. I want to read the slide switches and use the LED next to the slide switches to indicate which switch is in the on position.

Here is my code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


entity Switch is
   PORT(a,b,c,d: IN std_logic; 
     a_ON,a_Off,b_ON,b_Off,c_ON,c_Off,d_ON,d_Off: OUT std_logic);
end Switch;

architecture Behavioral of Switch is

begin
  PROCESS (a)
  begin
    if a = '1' then
      a_ON <= '1';
    else 
      a_OFF <= '1';
    end if;
 END PROCESS;   
end Behavioral;

Here is my *.ucf file:

NET "a" LOC = "L13" | IOSTANDARD = LVTTL | PULLUP ;
NET "b" LOC = "L14" | IOSTANDARD = LVTTL | PULLUP ;
NET "c" LOC = "H18" | IOSTANDARD = LVTTL | PULLUP ;
NET "d" LOC = "N17" | IOSTANDARD = LVTTL | PULLUP ;

NET "d_OFF" LOC = "F9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "d_ON" LOC = "E9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "c_OFF" LOC = "D11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "c_ON" LOC = "C11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "b_OFF" LOC = "F11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "b_ON" LOC = "E11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "a_OFF" LOC = "E12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "a_ON" LOC = "F12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;

Here is the errors I get:

PhysDesignRules:368 - The signal is incomplete. The signal is not driven by any source pin in the design.

ERROR:PhysDesignRules:368 - The signal is incomplete. The signal is not driven by any source pin in the design.

ERROR:PhysDesignRules:368 - The signal is incomplete. The signal is not driven by any source pin in the design.

ERROR:PhysDesignRules:368 - The signal is incomplete. The signal is not driven by any source pin in the design.

ERROR:PhysDesignRules:368 - The signal is incomplete. The signal is not driven by any source pin in the design.

ERROR:PhysDesignRules:368 - The signal is incomplete. The signal is not driven by any source pin in the design.

WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive any load pins in the design.

Solution

  • The following output ports in your design are not connected to any logic or driven in any way:

    b_ON,b_Off,c_ON,c_Off,d_ON,d_Off

    You need to drive them with at least '0' to pass DRC. for example:

    b_ON <= '0';

    If for some reason you really don't want to drive these signals, you could set them to mode inout, and drive them with 'Z':

    port (
  b_ON : inout std_logic
);

    ...

    b_ON <= 'Z';