In Kernel makefile $(call cmd, tags) what is the cmd here refers to?

In Kernel Makefile i found the code like below:

ctags CTAGS CSCOPE: $(HEADERS) $(SOURCES) 

$(ETAGS) $(ETAGSFALGS) $(HEADERS) $(SOURCES)

$(call cmd, ctags)

Also, where can i find the Macro or function ?

Solution

Using MadScientist's method on kernel v4.1:

make -p | grep -B1 -E '^cmd '

we find:

# makefile (from `scripts/Kbuild.include', line 211)
cmd = @$(echo-cmd) $(cmd_$(1))

scripts/Kbuild.include is included on the top level Makefile. It also contains:

echo-cmd = $(if $($(quiet)cmd_$(1)),\
    echo '  $(call escsq,$($(quiet)cmd_$(1)))$(echo-why)';)

quiet: set at the top level makefile, depending on the value of V.

Will be either:
- quiet_ to print CC file.c
- empty to print the command on V=
- silent_ to not print anything on make -s
escsq is defined as:
```
squote  := '
escsq = $(subst $(squote),'\$(squote)',$1)
```
It escapes single quotes so that echo '$(call escsq,Letter 'a'.' will print properly in sh.
echo-why: defined further down at Kbuild.include.

It is used for make V=2, and says why a target is being remade.

The setup of make tags is done in the Makefile:

quiet_cmd_tags = GEN     $@
      cmd_tags = $(CONFIG_SHELL) $(srctree)/scripts/tags.sh $@

tags TAGS cscope gtags: FORCE
    $(call cmd,tags)

Which shows the typical usage pattern for calling commands on kbuild:

quiet_cmd_XXX = NAME     $@
      cmd_XXX = actual-command $@

target: prerequisites
    $(call cmd,tags)

A comment on the Makefile explains how all of this is done to make the make output prettier:

# Beautify output
# ---------------------------------------------------------------------------
#
# Normally, we echo the whole command before executing it. By making
# that echo $($(quiet)$(cmd)), we now have the possibility to set
# $(quiet) to choose other forms of output instead, e.g.
#
#         quiet_cmd_cc_o_c = Compiling $(RELDIR)/$@
#         cmd_cc_o_c       = $(CC) $(c_flags) -c -o $@ $<