Modules in Verilog do not respond to input signals

Question

My current task is to create a memory driver. The specific issue is that I have a shift register designed to concatenate four 8-bit words into one 32-bit and then send that to the output. The module works when being simulated by itself but it fails to respond when connected to other modules. Here's the code :

The shift register code :

module shiftReg (

data_8,
clk,
valid1,
rstn,
data_32,
valid_fifo,
count,
REGA,
REGB,
REGC,
REGD
);

input wire [7:0] data_8;
input wire valid1;
input wire clk;
input wire rstn;
output reg [31:0] data_32;
output reg valid_fifo;
output reg [3:0] count;

output reg [7:0] REGA;
output reg [7:0] REGB;
output reg [7:0] REGC;
output reg [7:0] REGD;


initial 
begin
    count <= 4'b0001;
    REGA <= 8'b0;
    REGB <= 8'b0;
    REGC <= 8'b0;
    REGD <= 8'b0;
    valid_fifo <= 1'b0;
end

always @(posedge valid1)
begin
    if(~rstn)
        begin
            count = 4'b0001;
            REGA = 0;
            REGB = 0;
            REGC = 0;
            REGD = 0;
        end
else if(valid1 == 1'b1)
            begin
                case (count)
                    4'b0001: REGA = data_8;
                    4'b0010: REGB = data_8;
                    4'b0100: REGC = data_8;
                    4'b1000: REGD = data_8;
                endcase
                    valid_fifo = 1'b0;
            end
                if(count == 4'b1000)
                    begin

                        data_32 = {REGD,REGC,REGB,REGA};
                        valid_fifo = 1'b1;
                        count = 4'b0001;
                    end
            else 
                begin
                        count = count << 1;
                end
    end
endmodule

The module where I am instantiating it is called altogether. Here is the code :

module altogether (
input  wire BUTTON_AT,
input  wire CLK_AT,
input  wire RSTN_AT,
output wire MEM_FULL_AT,
output wire EMPTY_AT,
inout  wire VALID_IN_AT,
inout  wire [7:0] DATA_8_AT,
inout  wire VALID1_AT,
inout  wire [31:0] DATA_32_AT,
inout  wire STOP_AT,
inout  wire VALID_FIFO_AT,
inout  wire [31:0] DATA_AT,
inout  wire WR_AT,
inout  wire [6:0] ADDR_AT,
output wire [7:0] REG_A_AT,
output wire [7:0] REG_B_AT,
output wire [7:0] REG_C_AT,
output wire [7:0] REG_D_AT,
output wire [3:0] COUNT_AT
);

shiftReg shift_register (
.data_8(DATA_8_AT),
.clk(CLK_AT),
.valid1(VALID_1_AT),
.rstn(RSTN_AT),
.data_32(DATA_32_AT),
.valid_fifo(VALID_FIFO_AT),
.REGA(REG_A_AT),
.REGB(REG_B_AT),
.REGC(REG_C_AT),
.REGD(REG_D_AT),
.count(COUNT_AT)
);

For some reason, the valid == 1'b1 condition is not executed when I put the shift register along with everything else. I have really run out of ideas, hope someone manages to look at it and give me an insight.

Answer 1

Somewhere during synthesis you probably got warning that you're using VALID_1_AT signal, which has no driver. That's because in altogether module declaration you define VALID1_AT signal (notice _ missing in signal name). That's why valid1 in your shift register is not driven at all.

You should change:

.valid1(VALID_1_AT)

into:

.valid1(VALID1_AT)

to make it works.