Issue formatting "if" statement within testbench process?

Question

This has been driving me crazy. Here’s the code I have so far:

signal SYS_CLK : std_logic := '0';     --Input
signal InputSignal : std_logic := '0';  --Input

signal SyncOutputSignal : std_logic;     --Output

------------------------------------------------------
stim_proc:process(SYS_CLK)

begin   

      if (rising_edge(SYS_CLK)) then
          if (InputSignal = '1') then
             assert (SyncOutputSignal = '0') report "Bad Pulse..." severity ERROR; 
          end if;
      end if;

end process stim_proc;   

And a picture of the ISim waveform ---> i.imgur.com/G5KvCQe.jpg

The purpose of this test is to confirm that when on rising_edge(SYS_CLK) if InputSignal = '1', then a pulse is emitted (SyncOutputSignal) equivalent and in line to SYS_CLK's period.

However, an Error report is being issued everytime the CLK goes high and InputSignal is High.

Long story short, I need a way to tell the program to wait for the next InputSignal Pulse before testing the assert statement listed in my code again. Any ideas??

Answer 1

It sounds like you are trying to check for an edge condition on InputSignal. When checking for an edge condition in hardware, there's a simple thing you can do. Create a registered version of InputSignal (I called it Reg_InputSignal). Then change your if statement to check for a 1 on InputSignal and a 0 on Reg_InputSignal. This is a rising edge condition on InputSignal and should only trip the if statement for 1 clock cycle.

architecture RTL of Entity_Name is
  signal Reg_InputSignal : std_logic := '0';
begin
stim_proc : process(SYS_CLK)
begin
  if (rising_edge(SYS_CLK)) then
    Reg_InputSignal <= InputSignal;
    if (InputSignal = '1' and Reg_InputSignal = '0') then
      assert (SyncOutputSignal = '0') report "Bad Pulse..." severity error;
    end if;
  end if;
end process stim_proc;