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cnested-loopstexas-instrumentspipelining

Simple nested loop not pipelining on TI C64x+

The following code is not pipelining when compiled on the C64x+:

void main ()
{
    int a, b, ar[100] = {0};

    for (a = 0; a < 1000; a++)
        for (b = 0; b < 100; b++)
            ar[b]++;

    while(1);
}

My IDE (Code Composer v6) gives the following message for the inner loop: "Loop cannot be scheduled efficiently, as it contains complex conditional expression. Try to simplify condition."

The problem seems to be with the nested loop, but I can't find any more information about optimizing one as simple as this.

Has anyone solved a similar issue before?

-- Additional information --

  • Processor: TMS320C64x+

  • Compiler: TI v8.0.3

  • Compiler flags:-mv6400+ --abi=eabi -O3 --opt_for_speed=4 --include_path="D:/TI/ccsv6/tools/compiler/ti-cgt-c6000_8.0.3/include" --advice:performance -g --issue_remarks --verbose_diagnostics --diag_warning=225 --gen_func_subsections=on --debug_software_pipeline --gen_opt_info=2 --gen_profile_info -k --c_src_interlist --asm_listing --output_all_syms

  • Linker flags: -mv6400+ --abi=eabi -O3 --opt_for_speed=4 --advice:performance -g --issue_remarks --verbose_diagnostics --diag_warning=225 --gen_func_subsections=on --debug_software_pipeline --gen_opt_info=2 --gen_profile_info -k --c_src_interlist --asm_listing --output_all_syms -z -m"dsp.map" -i"D:/TI/ccsv6/tools/compiler/ti-cgt-c6000_8.0.3/lib" -i"D:/TI/ccsv6/tools/compiler/ti-cgt-c6000_8.0.3/include" --reread_libs --warn_sections --xml_link_info="dsp_linkInfo.xml" --rom_model

Solution

  • Removing --gen_profile_info from the compiler flags solved the issue. My loops have been splooped.