Why should I create a testbench/testbed in VHDL? Isn't it just as good to sit and manipulate the signals in the simulator to ensure that the VHDL code behaves correctly?
Solution
Create a testbench.
You can re-run it any time and extend it as the design grows.
You can make it self-checking - compare outputs with expected values, assert when anything's wrong, and report a summary of any errors.
You can use the full programming language to generate comprehensive tests, or random tests if the design is too large to test every input value
You can read files generated by Matlab or whatever, and write files of results to process and display in Matlab to prove its accuracy
You never need to pore through waveforms unless the self-checking reports an error, then display all the signals for further debugging.
You can make your testing semi- or even fully automatic.
Even if you do none of these, a minimal testbench that just drives the inputs and you have to examine the waveforms serves as the basis for something better later on.
(thanks to Morten) You can quickly modify an existing test case to recreate a reported bug in simulation, which gives you full visibility into signals and enables fixing much faster.
A VHDL testbench is usually portable, (reading/writing binary files is the one exception I know about, but text files are OK) so you aren't stuck using one specific toolchain.