Always loop Verilog

Question

This my Verilog code to convert the number x into form x=a0*R+a1 ,e.g 51 = 5*10 +1. My code does not work, it cannot enter the always loop.

`timescale 1ns / 1ps
module poly(
    input [15:0] r,
    input [15:0] x,
    output  reg[15:0] a1,
    output reg [15:0] a0,
    output finish,
    input clk,
    input reset
);

reg [15:0] sum;

assign finish =(sum > x);
always@ (posedge clk )
begin
    if(reset)
    begin 
        a0 <=0;
        sum <=0;
    end     
    else if (!finish)
    begin 
        a0 <=a0+1;
        sum <= sum+r;
    end
    else 
        a1<=x-sum;
end

initial begin
    $monitor ( "a1=%b,a0=%b,finish=%b,reset=%b",a1,a0,finish,reset);
end

endmodule 

testbench

`timescale 1ns / 1ps

module tb_p;

    reg [15:0] r;
    reg [15:0] x;
    wire[15:0] a1;
    wire [15:0] a0;
    wire finish;
    reg clk;
    reg reset;

    initial clk=0;
    always #5 clk=!clk;

    poly m1(r,x,a1,a0,finish,clk,reset);

    initial begin
        r<=10;
        x <=17;
        #1 reset<=1;
        #2 reset<=0;
    end

endmodule

Answer 1

Since your reset signal is synchronous to the clock, you need to extend it so that it is high for at least one posedge of the clock:

initial begin
    r<=10;
    x <=17;
    #1 reset<=1;
    #20 reset<=0;
    #500 $finish;
end

Note that I added $finish just so my simulation would end.