Convolution of signals using VHDL

I have been working on implementing convolution operation using VHDL in MultiSim Student PE Edition. The following code compiles successfully, however When I click Simulate i am getting the following error:

# vsim 
# Start time: 10:32:20 on Apr 26,2015
# Loading std.standard
# ** Error: (vsim-13) Recompile work.convolution because work.convolution has changed.
# 
# ** Error (suppressible): (vsim-12) Recompile work.convolution(behavioral) after work.convolution, work.convolution are recompiled.
# 
# Error loading design

Here is the source code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_arith.all;

package Convolution IS
    TYPE real_vector is ARRAY(integer RANGE <>) OF real;
end;

use work.Convolution.ALL;

entity convolution is
    port (x:in real_vector(0 to 3);
          h:in real_vector(0 to 1);
          y:out real_vector (0 to 4));
end convolution;



architecture Behavioral of convolution is
BEGIN   
    process (x,h)
    variable sum :real := 0.0;
    variable temp :integer := 0;

    begin
    for k in y'range loop
        sum:=0.0;
        for n in h'range loop
                temp := k-n;
            if temp >= 0 then
                sum := sum + h(n)*x(temp);  --we are assuming all singnals are positively indexed, negative indices deafult to 0.       
            end if;
            end loop;
            y(k) <= sum ;
    end loop;
    end process;
end Behavioral;

Help me with this issue please.

Solution

You have a name collision. You have two primary units in the same (working) library with the same name.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- use IEEE.std_logic_arith.all;

package Convolution_pkg IS
    TYPE real_vector is ARRAY(integer RANGE <>) OF real;
end;

use work.Convolution_pkg.ALL;

...

Change the name of one or the other. (This shows changing the package name).

You could alternatively analyze the convolution package into a different (e.g. it's own) library.

Using the same name in two primary units in the same library is a bit of a catch 22.

See IEEE Std 1076-2008, 13.5 Order of analysis paragraph 5:

A given library unit is potentially affected by a change in any library unit whose name is referenced within the given library unit. A secondary unit is potentially affected by a change in its corresponding primary unit. If a library unit is changed (e.g., by reanalysis of the corresponding design unit), then all library units that are potentially affected by such a change become obsolete and shall be reanalyzed before they can be used again.