I am trying to synthesize a code, there is no error but in map report I got this informational message as follows:-
INFO:LIT:244 - All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs in the schematic.
That message is just a "For your information" message because you are letting the tool automatically assign the default slewrate on all pins. It can be ignored. However, you will probably get rid of the warning if you explicitly specify the slewrate of your IOs instead of letting the tool assign the default slewrate. You can probably explicitly specify a SLOW slewrate for each pin, and get rid of the warning that way.
Here is the userguide for constraining IOs (slew is on page 251): http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_4/cgd.pdf As a FPGA developer you should absolutetly learn how to constrain IOs. It is a quite important. For each pin you should always specify properties such as: pin number, slew, IO-standard, pull-up/down/none resistor, current, and load.
Regarding selecting fast or slow slewrate. You shall always select the slowest possible slewrate which is fast enough for your design. While faster slewrate reduces delay by a nanosecond or so, that is the only advantage it has. But it has many disadvantages, particularly degraded signal quality in the form of ringing, electromagnetic emissions, and extremely high current surges when multiple pins change state at the same time. This can result in very difficult to debug stability problems, which you do not want.