page-tables
When do we need 3 level page table
If we have a machine with 64 bit address and each page table entry contains only a pointer to the assigned frame. How can I calculate the largest frame size possible if we need a three-level page table? I am so confuse about 3 level page table, under what circumstance do we need a 3 level page table? Any help would be appreciated.
Solution
Nested page tables can be implemented to increase the performance of hardware virtualization. By providing hardware support for page-table virtualization, the need to emulate is greatly reduced. For x86 virtualization the current choices are Intel's Extended Page Table feature and AMD's Rapid Virtualization Indexing feature.
Three-level page table structure in x86 architecture (with PAE, without PSE).
