How to pass parameters to a verilog module when performing synthesis?

Question

I have a parameterized verilog module with a bitwidth that is variable depending on the value given in `define WIDTH.

However, I would like to be able to somehow change the value of WIDTH by passing in a parameter during synthesis using design compiler.

I was wondering if there is a way to do this?

For instance, I'd like to be able to write the following for my input file for design compiler:

analyze -format sverilog -define WIDTH 10 myverilogfile.v

Answer 1

For Design Compiler the format is:

analyze -format sverilog -define WIDTH=10,DEPTH=128 myverilogfile.v