Testbench errors when using Xilinx Logicore Boxes

Question

I'm making a filter bank with user inputs, right now I'm trying to test this current design out, and see if anything needs to be fixed up. Currently, I can generate a bit stream and see my LED's change. However in the test-bench, the LED wave form does not move from it's initial zero state. Also, my filter does not seem to be working at all.

I used the LogiCore to make a FIR, and a DDS compiler to make a sine wave to stimulate it. And I am using a DSP48 to get amplitude modulation of the output signal.

I have the two ISim libraries I believe that I need. I' am not quite sure why my outputs are not being assigned?

I have looked at the documentation, and I am using Xilinx's ISIM, so I don't need to recompile the simulation libraries, I belive... am I wrong in thinking this?

There is a spot in the middle of my simulation where my data is present, I don't know if it's valid though.

Any help is apriciated.

My Top Module.

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    11:56:05 03/25/2015 
-- Design Name: 
-- Module Name:    Filter_Box - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.all;             

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Filter_Box is
    Port (  Board_Clock     : in    STD_LOGIC;
                --Filter_Clock  : in    STD_LOGIC;
                --Input_Sample  : in  STD_LOGIC_VECTOR (15 downto 0);
                --Out_data      : out STD_LOGIC_VECTOR (15 downto 0);
                led                 : out STD_LOGIC_VECTOR (3 downto 0);
                Mixer_Controls : in  STD_LOGIC_VECTOR (1 downto 0));
end Filter_Box;

architecture Behavioral of Filter_Box is

--
--  Component statements here, these should all be filters and/or DSP cores
--      unless otherwise noted.

--uses 1 dsp core and 1 bram
component Low_Pass
    port (
    clk : in std_logic;                             --core clock
    rfd : out std_logic;                                --filter ready for data flag
    rdy : out std_logic;                                --filter output ready flag
    din : in std_logic_vector(15 downto 0);     --data in (To be filterd)
    dout    : out std_logic_vector(15 downto 0));   --data out (has been filtered)
end component;


-- Uses 1 dsp core (3 dsp registers)
COMPONENT Mixer_controls_DSP_slice
  PORT (
    clk : IN STD_LOGIC;
    a : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
    b : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
    p : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
  );
END COMPONENT;


-- This sine wave box is for testing purposes only
COMPONENT Sine_Wave
  PORT (
    clk : IN STD_LOGIC;
    pinc_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
    sine : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
  );
END COMPONENT;


--
--  Singal instantiations
--
signal rfd  : std_logic;
signal rdy  : std_logic;
signal din  :   std_logic_vector (15 downto 0) := X"0000";
signal dout :   std_logic_vector (15 downto 0) := X"0000";
signal Low_Pass_Final_Data_Signal : std_logic_vector (15 downto 0) := X"0000";
signal pinc_in  : std_logic_vector (15 downto 0) := X"0001";


begin


--
--This register will controll all the singals
--      in the module and should direct the acctual
--      signals to their formal signals
Internal_Signal_Traffic_Controller : 
    process (Board_Clock) is 
        variable count : std_logic_vector (31 downto 0) := (others => '0');
    begin
    if rising_edge(Board_Clock) then
        led <= count(31) & count (30) & count(29) & count(28);
        count := count +1;
    end if;
end process;



--low pass filter instance, must use the filter clock,
--  currently filter clock is set to 500 MHZ
--      This will be the DSP clock as well
Low_Pass_Filter_Instance_Number_One : 
    Low_Pass port map (
            clk => Board_Clock,
            rfd => rfd,
            rdy => rdy,
            din => din,
            dout => dout);

-- Mixer instance to multiply filter outputs 
--      by fifo controll inputs, the output 
--      should then be passed to the adder core 
--  to reassemble the signal and put it out
--      to whichever port is needed
Filter_Instance_One_Amplitude_Controller : 
Mixer_controls_DSP_slice PORT MAP (
    clk => Board_Clock,
    a => Mixer_Controls,
    b => dout,
    p => Low_Pass_Final_Data_Signal
  );

-- This is the sinewave testing box
--      it should be deleted or commented
--          out after testing has been done
Sine_Wave_Testing_Box : Sine_Wave
  PORT MAP (
    clk => Board_Clock,
    pinc_in => pinc_in,
    sine => din
  );

--Out_data <= Low_Pass_Final_Data_Signal;


end Behavioral;

My Test bench

--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   14:00:04 03/25/2015
-- Design Name:   
-- Module Name:   D:/Dropbox/ECE.CLASSES/SeniorD/Filter_Top_Module/Filter_Box/Test_Bench_of_Filter_Module.vhd
-- Project Name:  Filter_Box
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: Filter_Box
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

library UNISIM;
use UNISIM.VComponents.all;

library UNIMACRO;  
use UNIMACRO.Vcomponents.all;


ENTITY Test_Bench_of_Filter_Module IS
END Test_Bench_of_Filter_Module;

ARCHITECTURE behavior OF Test_Bench_of_Filter_Module IS 

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT Filter_Box
    PORT(
         Board_Clock : IN  std_logic;
         --Out_data : OUT  std_logic;
         led : OUT  std_logic_vector(3 downto 0);
         Mixer_Controls : IN  std_logic_vector(1 downto 0)
        );
    END COMPONENT;


   --Inputs
   signal Board_Clock : std_logic := '0';
   signal Mixer_Controls : std_logic_vector(1 downto 0) := (others => '1');

    --Outputs
   signal Out_data : std_logic;
   signal led : std_logic_vector(3 downto 0);

   -- Clock period definitions
   constant Board_Clock_period : time := 10 ns;

BEGIN

    -- Instantiate the Unit Under Test (UUT)
   uut: Filter_Box PORT MAP (
          Board_Clock => Board_Clock,
          --Out_data => Out_data,
          led => led,
          Mixer_Controls => Mixer_Controls
        );

   -- Clock process definitions
   Board_Clock_process :process
   begin
        Board_Clock <= '0';
        wait for Board_Clock_period/2;
        Board_Clock <= '1';
        wait for Board_Clock_period/2;
   end process;


   -- Stimulus process
   stim_proc: process
   begin        
      -- hold reset state for 100 ns.
      wait for 100 ns;  

      wait for Board_Clock_period*10;

      -- insert stimulus here 

      wait;
   end process;

END;

Here is a waveform Example of what I get, and where my curious data is alive, but then goes back to being X's.

Edit: These DSP cores are designed to be driven at 500MHz and the filter has a sample frequency of 100KHz and a low-pass cutoff of 400Hz.

Answer 1

The FIR core from Xilinx doesn't accept and generate 1 sample per clock, but rather 1 every N clock cycles, where N depends on the parameters of the filter, particularly its length and architecture.

I recommend you to look at the FIR compiler datasheet, and start monitoring the signals rfd (ready for data, indicate when the input is read) and rdy (ready, indicate when the output is valid).