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vhdl

how to do zero padding al the lsb


I would like to add zero at the lsb (zero padding). my input is

 m  :   IN STD_LOGIC_VECTOR (31 DOWNTO 0);

and another vector (lets say a) that his length is changing all the time.
I didn't manage doing that by using bitwise "OR" because the length is always not the same.


Solution

  • Assuming you don't know the length of a, but want to zero pad the LSB of the resulting vector b it to length of b.

    b(b'left downto b'left - a'left) <= a;
    b(b'left - a'left - 1 downto 0) <= (others => '0');
    

    I hope I didn't mix up the - 1.