why aarch64 force qword aligned even transferred size is dword?

Below assembler code will cause "exc_bad_access code=259" on Xcode6.1.1 target on iPad air2.

    // SP default 16 aligned on function entry,
    sub sp,sp,#8
    st1 {v8.1d},[sp],#8

while new version will not

    sub sp,sp,#16
    st1 {v8.1d},[sp],#8

I find ARMv8_ISA document mention "aligned" on

chapter $3:unaligned address are permitted for most loads and stores,including...SIMD registers chapter $5.8.24.1:...a post-increment immediate offset,if present, must be 8/16/24/32/48/64, depending on the number of elements transferred.

Above code transferred size is dword(8bytes),why forcing qword aligned? BTW, I had not tested it on Android ndk r10, so I'm not confirm it's restrict on aarch64 or Xcode? Any suggestion? Thanks!

Solution

Are you sure it is the "st1" instruction that causes the crash?

You may check this using the following code:

sub sp,sp,#16
st1 {v8.1d},[sp],#16

I had a similar problem on x64; there it was another instruction which needed a properly aligned stack and caused the crash.

--- Edit ---

Sorry. I confused "[sp, #16]" and "[sp], #16".

If "[sp], #16" is post-increment then the test should look like this:

sub sp,sp,#16
st1 {v8.1d},[sp,#8]
add sp,sp,#8

Or:

sub sp,sp,#8
st1 {v8.1d},[sp]