Verilog FSM and module instantiation

Question

This finite state machine is to act as a controller for a datapath that contains the operators necessary to calculate the GCD of two 4 bit numbers. I am fairly new to this language and I am aware the issue is a probably a missing semi colon or maybe something with my declarations but I can't figure out what the problem is. I keep getting the errors:

ERROR:HDLCompiler:806 - "D:/Xilinx Stuff/GCD/GCD FSM.v" Line 44: Syntax error near "if". ERROR:HDLCompiler:806 - "D:/Xilinx Stuff/GCD/GCD FSM.v" Line 60: Syntax error near "=". ERROR:HDLCompiler:806 - "D:/Xilinx Stuff/GCD/GCD FSM.v" Line 64: Syntax error near "=". ERROR:HDLCompiler:806 - "D:/Xilinx Stuff/GCD/GCD FSM.v" Line 68: Syntax error near ";".

I'm also open to any tips regarding the logic in general,the code for the FSM is shown below:

module GCD_FSM(clk,data_in,reset,data_out,x_in,y_in,gcd_out,xgty,xlty,xequaly,go_in,xnew,ynew);

    input   clk, data_in, reset,go_in;
    input reg[3:0] x_in,y_in,gcd_out;
    output reg [1:0] data_out;
    reg [3:0] x,y;
    output reg[3:0] xnew,ynew;
    output reg xgty,xlty,xequaly,cleango;

    // Declare state register
    reg [1:0]state;

    // Declare states
    parameter S0 = 0, S1 = 1, S2 = 2, S3 = 3, S4 =4;

    /* Output depends only on the state
    always @ (state) begin
        case (state)
            S0:
                data_out = 2'b01;
            S1:
                data_out = 2'b10;
            S2:
                data_out = 2'b11;
            S3:
                data_out = 2'b00;
            default:
                data_out = 2'b00;
        endcase
    end
    */


    // Determine the next state
    always @ (posedge clk or posedge reset) begin
        if (reset)
            state <= S0;
        else
            case (state)
                S0:
                    debounce start(.clock(clk),.noisy(go_in),.clean(cleango));
                    if (cleango)
                        state <= S1;
                    else
                        state <= S0;
                S1:
                    state <= S2;
                S2:

                    if (xlty)
                        state <= S3;
                    else if(xgty)
                        state <= S4;
                    else if(xequaly)
                        state <= S5;
                S3:
                    ripple_carry_adder_subtractor ysubx(.S(ynew),.C(carry),.V(overflow),.A(y),.B(x),.Op(1));
                    y = ynew;
                    state <= S2;
                S4:
                    ripple_carry_adder_subtractor xsuby(.S(xnew),.C(carry),.V(overflow),.A(x),.B(y),.Op(1));
                    x = xnew;
                    state <= S2;
                S5:
                    gcd_out = x;
                    state <= S0;

            endcase
    end

endmodule

Answer 1

A few errors that I noticed:

• Line 3, you are missing a ; at the end: output reg[3:0] gcd_out
• Variables go_in and cleango are not defined.
• Module debounce is not defined