VHDL: Trouble combining entities (components)

Question

Me again!

I wrote something SUPER simple in order to demonstrate how entities come together. However, I'm having trouble figuring out why the output of the combined entities never assumes any value (other than U). Here's the code (its super simple, I promise!)

library ieee;
use ieee.std_logic_1164.all;

entity OR_LOGIC is
    port(
        in_a  : in  std_logic;
        in_b  : in  std_logic;
        out_c : out std_logic
    );
end entity;

architecture OR_LOGIC_ARCH of OR_LOGIC is
begin
    out_c <= in_a or in_b;
end OR_LOGIC_ARCH;


library ieee;
use ieee.std_logic_1164.all;

entity AND_LOGIC is
    port(
        in_a  : in  std_logic;
        in_b  : in  std_logic;
        out_c : out std_logic
    );
end entity;

architecture AND_LOGIC_ARCH of AND_LOGIC is
begin
    out_c <= in_a and in_b;
end AND_LOGIC_ARCH;


library ieee;
use ieee.std_logic_1164.all;

entity COMBO is
    port(
        in_a  : in  std_logic;
        in_b  : in  std_logic;
        in_c  : in  std_logic;
        out_d : out std_logic
    );
end entity;

architecture COMBO_ARCH of COMBO is
    signal wire1 : std_logic;
    signal wire2 : std_logic;
    component OR_LOGIC
        port(
            in_a  : in  std_logic;
            in_b  : in  std_logic;
            out_c : out std_logic
        );
    end component;
    component AND_LOGIC
        port(
            in_a  : in  std_logic;
            in_b  : in  std_logic;
            out_c : out std_logic
        );
    end component;
begin

    or1 : OR_LOGIC port map (in_a, in_b, wire1);
    and1 : AND_LOGIC port map(in_c, wire1, wire2);
end COMBO_ARCH;

and then:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity TEST_ENTITY is
end entity TEST_ENTITY;

architecture TEST_ENTITY_ARCH of TEST_ENTITY is    
    component ANDandOR
        port(
            in_a  : in  std_logic;
            in_b  : in  std_logic;
            in_c  : in  std_logic;
            out_d : out std_logic
        );
    end component; 
    signal in_a, in_b, in_c, out_d : std_logic;

begin

    combination : ANDandOR port map (in_a, in_b, in_c, out_d);

    process
    begin
        in_a <= '0';
        in_b <= '0';
        in_c <= '0';
        wait for 5ns;

        in_a <= '1';
        in_b <= '0';
        in_c <= '1';
        wait for 5ns;

        in_a <= '0';
        in_b <= '1';
        in_c <= '0';
        wait for 5ns;
    end process;

end architecture TEST_ENTITY_ARCH;

Answer 1

First, you have assigned the output of your AND gate to wire2, but wire2 is floating. You should either assign it to your ouput like this

out_d <= wire2;

OR remove wire2 from your internal signals and assign your output directly.

and1 : AND_LOGIC port map(in_c, wire1, out_d);

Second, your test bench needs to have the proper name of the component COMBO in order to map it properly. Quartus can generate a test bench template for you, that you can then add test code to it.

Processing --> Start --> Start Test Bench Template Writer

It comes very handy :)