Let's say I have a code:
wire clk1;
wire clk2;
assign clk1 = Clk;
assign Clk2 = Clk;
Now clk1 and clk2 are used to clock various modules and traverse through the hierarchy of the design. Somewhere deep in the hierarchy, if a module is clocked by clk1, does it's output remain synchronous with another from module2?
e.g.
reg r1;
always @ (posedge clk1)
r1 <= rSomething;
reg r2;
always @ (posedge clk2)
r2 <= r1;
Is this code valid? Will the synthesis tools (Altera tool chain) maintain the skew across these two clocks? Or will it maintain the skew only on clocks that are named the same and clk1 and clk2 will cease to be synchronous despite their common source?
Thanks
EDIT1 : This for synthesis, not simulation.
EDIT2: Changed the second code example. I was trying to assign r2 <= r1, not the other way round as we the case earlier.
A synthesizer will transform your design input into an internal netlist that represents the logic structure. This is typically done in two stages. First to a high level behavioral form that represents abstract operations and then to a technology mapped form that directly implements logic primitives of the target architecture. In this transformation process clk1 and clkl2 will be seen as topologically equivalent to clk and they will be treated as one combined net.
The normal clock buffer insertion process will account for the skew across all leaf nodes in the unified net. Any timing constraints would need to be put on clk. An attempt to constrain clk1 and clk2 independently could have unpredictable results.