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linux-kernelarmpower-managementcpu-cache

what is clean state in L2 cache?

In ARM architecture while reading the CPU shutdown sequence I found these steps:

  1. save per CPU peripherals (IC, VFP, PMU)
  2. save CPU registers
  3. clean L1 D-cache
  4. clean state from L2
  5. disable L1 D-cache allocation
  6. clean L1 D-cache
  7. exit coherency
  8. call WFI (wait for interrupt)

What does clean L1 mean? Does it means delete all the content of L1? And what does clean state from L2 means?

Solution

  • What is clean?

    Clean, in ARM Cortex-A documents, usually means a flush (write dirty cache lines to next level). It is only valid for Dcache or unified caches. Some times we need both clean and invalidate (clear the cache). This is important if some other entity (bus master/peripheral) may change the memory. Usually, a bus (AXI) has a mechanism to avoid this. Also, if you update code in main memory and there is previous I-cache data, you need to invalidate it.

    Why multiple cleans?

    You need to clean the L1 to make sure the data is in the L2 (flushed) so that you may then clean the L2. As we disable the L1 DCache, you may have some stale data from the act of L2 flushing in the L1. I am not completely sure why they say clean as opposed to invalidate for step 6. You haven't given an exact ARM CPU and these details vary depending on the type. It seems this is maybe an Cortex-A5/A8/A9 with external L2C-310.

    The 2nd L1 clean is due to a race between the two levels of caches. It is describe in one of the Cortex-A technical reference manuals (TRM). I would follow their advice as it probably avoids some rare corner case and this type of code is difficult to debug. Shutdown/suspend/sleeping by necessity disables all your debug devices and is difficult to trouble shoot like boot code.