Non resolved signal has multiple sources VHDL

Question

i am implementing a simple FSM using VHDL . I came out with this code in VHDL and i got this error:'non resolved signal NS has multiple sources'.I looked deeply in the code but coudln't figure out the mistake Can anyone help me to solve this problem?

                     library ieee ;
                     use ieee.std_logic_1164.all ;
                     entity MeallyMachine is
                     port( 
                     x,res,clk:in std_logic;
                     z1,z2:out std_logic       
                     );

                    end MooreMachine;


                    architecture M1 of MooreMachine is
                    type state_type is(s0,s1,s2,s3);
                    signal PS,NS:state_type;

                     begin
                     ETAT:process(PS,x)
                     begin
                     case PS is
                      when  s0=>  if (x='0') then
                      NS<=s0;
                                 elsif (x='1') then
                                 NS<=s1;
                                 end if;
                     when s1=>  if (x='0') then
                      NS<=s1;
                                elsif (x='1') then
                      NS<=s2;
                                end if;  
                     when s2=>  if (x='0') then
                     NS<=s2;
                                elsif (x='1') then
                     NS<=s3;
                                 end if;
                     when s3=>  if (x='0') then
                     NS<=s3;
                                 elsif (x='1') then
                     NS<=s0;
                                 end if;
                     end case;
                   end process ETAT;
                Sortie:process(PS,x)
                  begin
                   case PS is
                      when s0=>  
                            z1<='1';
                        if (x='0') then
                            z2<='0';
                         elsif (x='1') then
                            z2<='1';
                          end if;
                      when s1=>   
                            z1<='1';
                       if (x='0') then
                            z2<='0';
                       elsif (x='1') then
                        z2<='1';
                       end if;  
                     when s2=>  z1<='0';
                      if (x='0') then
                        z2<='0';
                      elsif (x='1') then
                        z2<='1';
                      end if;
                   when s3=>   z1<='1';
                        if (x='0') then
                         z2<='0';
                        elsif (x='1') then
                         z2<='1';
                        end if;
                   end case;
                end process Sortie;
           Horloge:process(clk,res,NS)
                begin
                 if (res='0') then
                      NS<=s0;
                 elsif (rising_edge(clk)) then 
                      PS<=NS;
                 end if;
                 end process Horloge;




         end M1;

Answer 1

Your error message: non resolved signal NS has multiple sources contains also the source lines, which causes the multiple driver issue. See the full Xilinx XST synthesis report.

More over, your code has multiple copy-paste errors:

1. entity MeallyMachine is should be entity MooreMachine is because your architecture references MoorMachine
2. NS<=s0; should be PS<=s0; to solve the multiple driver problem
3. Your FSM is not a Moore FSM, because the outputs depend on current state and inputs process(PS,x)