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c++variablesmakefileprerequisites

How to expand makefile variable in prerequisites list?

I am having an issue defining a prerequisites for my targets while using file lists in variables the problem is as follows:

in my makefile:

... some basic defines
SOURCES=HelloC.cpp \
        HelloS.cpp \
        HelloI.cpp \
        main.cpp
SOURCES_CLIENT=Hello_Client_impl.cpp \
               HelloC.cpp
OBJECTS_SERVER_DIR=obj_s/
OBJECTS_CLIENT_DIR=obj_c/
OBJECTS_SERVER=$(addprefix $(OBJECTS_SERVER_DIR),$(SOURCES:.cpp=.o))
OBJECTS_CLIENT=$(addprefix $(OBJECTS_CLIENT_DIR),$(SOURCES_CLIENT:.cpp=.o))
EXECUTABLE_SERVER=server
EXECUTABLE_CLIENT=client

all: dirs server_exe client_exe

dirs:
  @echo create dirs
  $(CREATE_DIR) $(OBJECTS_SERVER_DIR)
  $(CREATE_DIR) $(OBJECTS_CLIENT_DIR)

server_exe: $(EXECUTABLE_SERVER)

client_exe: $(EXECUTABLE_CLIENT)

$(EXECUTABLE_SERVER): $(OBJECTS_SERVER)
  $(CXX) $^ $(LFLAGS) $(LIBS) -o $@

$(EXECUTABLE_CLIENT): $(OBJECTS_CLIENT)                                                                                                                                                                                                        
  $(CXX) $^ $(LFLAGS) $(LIBS) -o $@

# problematic line 1    
$(OBJECTS_SERVER): $(SOURCES)
  $(CXX) -c $(CPPFLAGS) -o $@ $<

# problematic line 2
$(OBJECTS_CLIENT): %.o : %.cpp
  $(CXX) -c $(CPPFLAGS) -o $@ $<

Running it (as dry run) I will get:

$ make -n
echo create dirs
mkdir -p obj_s/
mkdir -p obj_c/
g++ -c -Wall -I. -I/usr/include/ -I/usr/include/orbsvcs/ -I/usr/include/tao/ -I/usr/include/tao/PortableServer/ -o obj_s/HelloC.o HelloC.cpp
g++ -c -Wall -I. -I/usr/include/ -I/usr/include/orbsvcs/ -I/usr/include/tao/ -I/usr/include/tao/PortableServer/ -o obj_s/HelloS.o HelloC.cpp
g++ -c -Wall -I. -I/usr/include/ -I/usr/include/orbsvcs/ -I/usr/include/tao/ -I/usr/include/tao/PortableServer/ -o obj_s/HelloI.o HelloC.cpp
g++ -c -Wall -I. -I/usr/include/ -I/usr/include/orbsvcs/ -I/usr/include/tao/ -I/usr/include/tao/PortableServer/ -o obj_s/main.o HelloC.cpp
g++ obj_s/HelloC.o obj_s/HelloS.o obj_s/HelloI.o obj_s/main.o -L/usr/lib64/ -lTAO_PortableServer -lTAO_AnyTypeCode -lTAO -lACE -o server
make: *** No rule to make target `obj_c/Hello_Client_impl.cpp', needed by `obj_c/Hello_Client_impl.o'.  Stop.

problematic line 1 will not expand and will always keep the first source file (HelloC.cpp) as a parameter while the second one is defined with prefix. How can I handle this so that it compiles? I would like to have source files in root dir and object files in obj_c and obj_s directories

Solution

  • EDIT: I originally answered the wrong question in haste, sorry about that. Anyway, the static pattern rule is the way to go, but you have to factor in the prefix. Instead of

    $(OBJECTS_CLIENT): %.o : %.cpp

    Use 

    $(OBJECTS_CLIENT): $(OBJECTS_CLIENT_DIR)%.o : %.cpp