assign output array correctly

Question

How do I assign a input-bus to an output-bus without having to assign every index (without loops).

I had something like that in mind:

module test(input [2:0] in, input CLK, output [2:0] out);
reg [2:0] state;
always @(posedge CLK) state <= in; 
assign out = state;

But this code doesn't work. I need : out[0] = in[0], out[1] = in[1], out[2] = in[2].

Answer 1

Issues with the giving code:

• CLK is defined as a 3-bit input, should be 1-bit
• Missing semicolon (;) on the first line
• Missing keyword endmodule

FYI: By declaring out as an output reg the intermediate state can be omitted.

module test (
    input      [2:0] in,
    input            CLK, // <-- CLK is single bit
    output reg [2:0] out // <-- out is a reg type
    ); // <-- semicolon here

  always @(posedge CLK)
    out <= in; // <-- synchronous assignment

endmodule // <-- keyword