Talking with respect to GNU make, what is the difference between PHONY targets all: and default:.
CC=g++
default: hello
hello: hello.cpp
$(CC) -o hello hello.cpp
and
CC=g++
all: hello
hello: hello.cpp
$(CC) -o hello hello.cpp
Both of them do the same job.
You can call them shirley if you like; neither of the labels you mention has any special semantics. The default behavior of make is to run the first target in the Makefile if you don't specify a target as a command-line argument. If you like to override this behavior, there is the .DEFAULT_GOAL special variable.
There is a convention to have a target named all which builds everything, but this is just human convention, not a special case or a requirement as far as Make is concerned.
Similarly, there is a (weak) convention to call the default target default, but similarly, this is just a human label (and somewhat overlaps and possibly conflicts with the all convention).
So the following Makefile does exactly the same thing:
.PHONY: shirley all default
default: hello
all: hello
shirley: hello
hello: hello.cpp
# (Make already knows how to build an executable out of a .cpp file)
You can omit any or all of the phony targets above, and the only difference will be that humans won't be able to say make shirley when they (effectively) mean make hello.
Bottom line: Construct your Makefile so that make does what a reasonable end-user expects without reading too much README files or inspecting the Makefile. Often that will be make all (and you should probably have a target with this name, just to satisfy human conventions, even if it's not the default) but this obviously depends on your project and your users' expectations.
Don't call me Shirley.