VHDL - Increment with one (unsigned)

Question

I'm trying to make a code that will increment the incoming bits with one. I want to use two-segment code styling, but the issue here is that the bits don't reach the output. Any idea? Thanks!

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;


entity increment1 is
    port(
        from_ASMD_State_reg : in std_logic_vector(7 downto 0);
        reset, clk : in std_logic;
        to_mux : out std_logic_vector(7 downto 0)
    );
end increment1;

architecture Behavioral of increment1 is
--signal count : unsigned(7 downto 0);
signal r_reg : unsigned(7 downto 0);
signal r_next : unsigned(7 downto 0);
begin
process(clk, reset)
begin
    if(reset = '1') then
        to_mux <= (others => '0');
    elsif(clk'event and clk = '1') then
        r_reg <= r_next;
    end if;
end process;

r_next <= r_reg + 1;

to_mux <= std_logic_vector(r_reg);

end Behavioral;

After some adjustments in code, it seems like it's working now!

architecture Behavioral of increment1 is
signal r_reg : unsigned(7 downto 0);
signal r_inc : unsigned(7 downto 0);
begin
process(clk, reset, r_reg)
begin
    r_reg <= unsigned(from_ASMD_State_reg);

    if(reset = '1') then
        r_reg <= (others => '0');
    elsif(clk'event and clk = '1') then
        r_reg <= r_inc;
    end if;
end process;

r_inc <= r_reg + 1;

to_mux <= std_logic_vector(r_inc);

end Behavioral;

Answer 1

your updated code is almost correct, but not quite. If all you want to do is increment and register a value, all you need is this:

architecture Behavioral of increment1 is
begin

  r_inc <= unsigned(from_ASMD_State_reg) + 1;

  process (clk, reset)
  begin
    if(reset = '1') then
        r_reg <= (others => '0');
    elsif(clk'event and clk = '1') then
        r_reg <= r_inc;
    end if;
  end process;

  to_mux <= std_logic_vector(r_reg);

end Behavioral;

(note: edited the above to fix an assignment mistake and reorder the statements to make the desired "two segment style" more obvious)

Are you sure it "works" with the assignment to r_reg inside your process but outside the if block? Have you tried to synthesize, or only simulate?

Optimizations:

• You can get rid of r_inc by putting the increment statement directly into the r_reg assignment in the process.
• You can get rid of r_reg by replacing it with to_mux in the process and typecasting.

You don't need all those intermediate signals for this operation. If you need them for other functions you want to add, feel free to keep them, but just be aware that the ports can be used in these operations - you don't need to assign them to another signal first.

The simplified assignment in your process would then be:

to_mux <= std_logic_vector(unsigned(from_ASMD_State_reg) + 1);

It's barely worth making a separate component to do this, but you can, of course.