Shifting and adding a std_logic_vector (has 36 but must have 18 elements)

Question

I'm facing some weird errors from quartus when I try this.

Here's the code (all the unsigned & other weird functions was my attempt at persuading Quartus to compile it.)

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

...
variable data : std_logic_vector(17 downto 0) := "000000000000000011";

...

-- 00000000111111000 original
-- 00000000000011111 shifted
-- 00000000000011000 result (AND)

data := std_logic_vector(unsigned(data) & shift_right(unsigned(data), 4));


-- 00000000011111000 original
-- 00000000111110000 shifted
-- 00000000111111000 result (OR)

data := std_logic_vector(unsigned(data) or shift_left(unsigned(data), 1));

I've left out quite a lot of the code, but the broken parts are left the same.

I'm getting

Error (10344): VHDL expression error at snake_driver.vhd(66): expression has 36 elements, but must have 18 elements

How to do it right?

Answer 1

The & operator is not the same as the and operator in VHDL. You are looking for the and operator to perform a bitwise and operation. & is the concatenation operator on vectors and using it between two 18-bit vectors will produce a 36-bit vector (and likewise a vector width mismatch) as indicated by your error message.