A if condition in VHDL can be implemented using a MUX. But I want my MUX's output to vary when there is a rising edge for the clock. I really wanted to give clock and clk'event as the select line for my MUX.
signal a:std_logic;
process(clk)
a <= clk and clk'event;
o <= (a and s1) or ((not a) and s2);
end process;
But this would give me an error because of clk'event. I tried with clk'stable. But since clk'stable is a boolean signal, it would give me an error. There is no type conversion for this either. Is there any other alternative for a PURE STRUCTURAL implementation rather than a behavioral one?
Presumably clk is a std_logic type signal.
Without seeing your actual error message the line in question is:
a <= clk and clk'event;
The 'event attribute returns a type BOOLEAN. clk appears eligible for an implicit condition operator (??), IEEE Std 1076-2008) which also returns a type BOOLEAN.
Unfortunately the assignment to a is done with an implicitly declared signal assignment for the base type of std_logic (std_ulogic), a basic operation and requires the input type matches the target type.
VHDL is strongly typed and you can't assign a BOOLEAN to a std_logic without type conversion.
Also the assignment to a would be a one delta cycle long, effectively a glitch or a pulse.
It isn't clear it has any useful meaning in synthesis.
The output o would be s1 during a = '1', otherwise s2, except for the sensitivity list not including a.
You can demonstrate the single delta cycle long pulse in simulation by using a different assignment type, such as a conditional signal assignment:
a <= '1' when clk = '1' and clk'event else
'0';
Where as a concurrent conditional assignment the condition results in a BOOLEAN and the target is a '1' enumeration literal compatible with std_logic when the condition is TRUE, or a '0' enumeration literal when FALSE.
Because a isn't in the sensitivity list for the process as a sequential conditional signal assignment o will always be s2.
And if you're using a VHDL tool compliant to and older standard the conditional signal assignment statement won't work in the process.
You could make both assignment statements concurrent signal assignments where they'd end up as separate equivalent processes with the appropriate sensitivity list equivalents (a wait statement as the last statement of each).