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cachingcpu-architecturecpu-cachelru

Cache bits per row and total length


If i have a

32bit address

,

cache size(c) 8 KB

,

Block Size(b) 16 B

,

Set Associativity(a) 1

its a Direct Mapped Cache what would be the bits per line in cache? including dirty bit and validity bit. what would be the total no of lines in cache?

some idea which i got via searching on internet is

offset bits = log b = 4 bits
index bits = log c/b * 1024 = 9 bits
tag bits = 32 - offset - index = 19 bits
validity and dirty would have 1, 1 bit

still confused that how i will calculate size of cache or how many lines this cache would have?


Solution

  • Your Internet search gave you the right answer.

    • Block size of 16 bytes -> need 4 bits to specify the offset within the block.
    • 8K byte cache and 16 byte lines -> 512 blocks. (8K / 16 = 512)
    • Direct mapped cache -> 512 / 1 way set associativity = 512 sets
    • 512 sets -> need 9 bits for the index (512 = 2^9)

    With a 32 bit address, if 4 bits are used for the block offset and 9 for the index that means that the remaining 19 bits are needed for the tag.

    Since this is a direct map cache, no bits are needed for a replacement policy (e.g. LRU). You'll need at least one bit for validity. With 2 bits you can implement a cache coherence algorithm like MESI. So figure 20 to 21 bits are needed per block.