Seven Segment Decoder

Question

So I'm trying to design Seven Segment Decoder. When Button is pressed at 110, then the LED Display should display 1 digit hex number: 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F. But, when Button is pressed at 101, then the LED Display should display 1 digit decimal number: 0,1,2,3,4,5,6,7,8,9.

This is my Warnings:

Xst:737 - Found 1-bit latch for signal <out<4>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
Xst:737 - Found 1-bit latch for signal <out<5>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
Xst:737 - Found 1-bit latch for signal <out<3>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
Xst:737 - Found 1-bit latch for signal <out<2>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
Xst:737 - Found 1-bit latch for signal <out<1>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
Xst:737 - Found 1-bit latch for signal <out<0>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
Xst:737 - Found 1-bit latch for signal <out<6>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

This is my code using Xilinx design tools:

module hex_sch(out, in, button);
output reg [6:0] out;
input [3:0] in;
input [2:0] button;
// Low active signal should activate the LEDs
    always @(button or in) 
    begin
        if (button == 3'b110) begin
            case (in)
            //Output format gfedcba
            4'h0: out <= 7'b1000000;
            4'h1: out <= 7'b1111001;
            4'h2: out <= 7'b0100100;
            4'h3: out <= 7'b0110000;
            4'h4: out <= 7'b0011001;
            4'h5: out <= 7'b0010010;
            4'h6: out <= 7'b0000010;
            4'h7: out <= 7'b1111000;
            4'h8: out <= 7'b0000000;
            4'h9: out <= 7'b0011000;
            4'hA: out <= 7'b0001000;
            4'hB: out <= 7'b0000011;
            4'hC: out <= 7'b1000110;
            4'hD: out <= 7'b0100001;
            4'hE: out <= 7'b0000110;
            4'hF: out <= 7'b0001110;
            default: out <= 7'bx;
            endcase
            end
        else if (button == 3'b101) begin
            case (in)
            //Output format abcdefg
            4'd0: out <= 7'b1000000;
            4'd1: out <= 7'b1111001;
            4'd2: out <= 7'b0100100;
            4'd3: out <= 7'b0110000;
            4'd4: out <= 7'b0011001;
            4'd5: out <= 7'b0010010;
            4'd6: out <= 7'b0000010;
            4'd7: out <= 7'b1111000;
            4'd8: out <= 7'b0000000;
            4'd9: out <= 7'b0011000;
            default out <= 7'bx;
            endcase
            end
    end
endmodule

Answer 1

In order to remove those warnings you must set a value for out in every possible in and button. otherwise you will get a latch.

In your code you do not cover all posibilities for button input - you only cover 110 and 101.

An easy way to cover all posibilities in your code may be:

... // your module definition as is

// Low active signal should activate the LEDs

always @(button or in) 
begin
    if (button == 3'b110) begin
        case (in)
        //Output format gfedcba

... // your case statement as is

        endcase
    end
    else if (button == 3'b101) begin
        case (in)

... // your case statement as is

        endcase
    end
    else begin
        out <= 7'b1;
    end
end endmodule

This way, when button is different then 110 or 101, it will show blank.