Pipeline hazard handling with store

Question

Consider the following execution of instructions in a 5-stage pipeline (IF - ID - EX - MEM - WB) where "SD N(R2), R1" means store data from register R1 to memory position M[N+R2], "ADD R3, R1, R2" performs the operation R1 + R2 and stores the result in R3, and NOP is a bubble.

For what I understand registers are read on the ID stage.

So, if I have the following instructions:

I1: SD 0(R2), R6
NOP
I2: ADD R3, R1, R2

then the execution goes as following (I hope it looks clear)

         R2 is read
             ^     Store M[0+R2] <- R6
             ^          ^
I1:   | IF | ID | EX | MEM | WB |
NOP:       |////|////|////|////|////|
I2:             | IF | ID | EX | MEM | WB |
                        v
                     R2 is read

Is there a hazard on the 4th cycle when I1 is on the MEM stage and I2 on the ID stage because both instructions want to access R2 at the same time? Or is there no hazard since R2 is only read on the ID stages and therefore it is not accessed on the MEM stage?

Answer 1

All registers are read in the ID stage, thus there are no hazards in trying to read registers.

This does mean that some instructions will have to stall in ID if the registers they want to read aren't finished yet. That's where "bypassing" can help.