Need help to figure out how the CLB of a FPGA is built (on this drawing)

Question

there is a drawing of a configurable logic block(CLB) of a FPGA I am trying to figure out:
_{(source: eet.com)}

So, my questions are:
1. What is the green rectangle and what does it do?
2. What is DIN (C2) and EC (C4)? Is EC the same as CE (clock enable)?
3. Why is there a need for SET in this kind of flip flop (I'm assuming C3 S/R is SET/RESET). I mean, there is already the D input as the data we want to "save" and the RD is the reset - then what is the role of SD?

Help, please? :)

Answer 1

Not knowing the specific FPGA architecture, the below is based on a likely interpretation of the drawing:

1. The SD and RD on on flip-flops are asynchronous set and reset, and the green boxes are control for these depending on the S/R (C3) input to the CLB. The green box control is then configured in one of the ways:

   • from S/R to SD, with inactive RD

   • from S/R to RD, with inactive SD

   • no S/R connection thus inactive SD and RD if asynchronous set/reset are unused

2. DIN and EC:

   • DIN (C2) is some extra and fast interconnect data from other CLBs, so this data does not have to go use the logic function on the left.

   • EC (C4) is is enable clock for the flip-flops, which is used depending on the configuration of M3 and M7 muxes.

3. Some FPGA architectures have both asynchronous set and reset, and some do only have one of these for example the asynchronous reset. The functionality of asynchronous set operation may be required depending on the logical levels in the design, but if only asynchronous reset is available, then the data output is inverted using a logic function, so both types of reset are typically not required.