VHDL syntax error near while

Question

I wrote a VHDL code to find gcd of two numbers. However while compiling it's giving me the following error

near "while": syntax error

The code is

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity gcd is
port(a,b:in integer;
    c:out integer);
end gcd;

architecture gcd of gcd is
    function calc_gcd(a,b:integer) return integer is
    while a/=b loop
        if a>b then
            a:=a-b;
        else
            b:=a-b;
        end if;

    end loop;

    return m;
    end calc_gcd;
begin
process(a,b)
begin
gcd<=calc_gcd(a,b);
end process;
end gcd;

I checked the syntax. It seems correct. What's wrong?

PS : I use ModelSim Student edition

Answer 1

You are missing a begin statement for your function.

There's a couple of other errors.

You're trying to assign to an input argument (a and b). Arguments to a function are copied onto the stack. You could use a procedure, but it looks like you really want a local variable.

There is no declaration for m. That's the one (a local variable).