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Compilation error in Vivado

I downloaded Vivado free Web Pack and try to simulate the simple project like this:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity async_RS_trig is
    Port ( R : in  STD_LOGIC;
           S : in  STD_LOGIC;
       Q : out  STD_LOGIC;
       nQ : out  STD_LOGIC);
end async_RS_trig;
architecture async_RS_trig of async_RS_trig is
    signal bQ,nbQ : std_logic;
begin
    bQ <= R nor nbQ;
    nbQ<= S nor bQ;
    Q   <= bQ;
    nQ  <=  nbQ;
end async_RS_trig;

When I push Run simulation Vivado try to compile this code and I receve the error:

ERROR: [XSIM 43-3409] Failed to compile generated C file       xsim.dir/async_RS_trig_behav/obj/xsim_0.c.

But code is right, I tried to simulate an empty architecture and receved same error. What have I do to fix it?

Thank you! Regards

Solution

  • Resolved. This are few steps which you have to check:

    1. I don't know about drive, but directory name don't have commas in it name and may be another bad :) symbols. The best folder to install is C:\xilinx :)
    2. Full uninstall Comodo internet security, because switch off didn't help and made some another troubles.
    3. I read about including Xilinx, Xilinx license and Projects folders to antivirus exceptions, but I didn't made this

    I hope it will help to someone :)