Search code examples
inputoutputvhdl

VHDL Input & output code

I just started with VHDL so this is hopefully a pretty basic question, My problem is that i want to code this ciruit! --> http://postimg.org/image/rrd2czsox/ <--

In my ciruit as u can see, p and q both acts as input & outputs signal. Here is my code for this ciruit! 

library ieee;
use ieee.std_logic_1164.all;


entity pracc is

port(a,b,s,p,q : in std_logic;
        y,z: out std_logic);

end pracc;

architecture Exercise5 of pracc is

begin 

p <= a AND b;
q <= NOT p;
y <= p;
z <= q;

end architecture;

But i can't compile this. Even if i change p & q as output signals!

Glad for help!

Solution

  • p and q are not inputs to your overall circuit - they're intermediate/local signals. Declare them like so:

    architecture ...
  signal p,q : std_logic;
begin
...

    Local signals connect logic within a component. Ports connect your component to other things.