I am trying to understand the protection provided by intel x86 MMU architecture. I am confused basically as to when will the MMU raise the page fault(page_fault, int 14) and when will the CPU raise an exception (general_protection fault, int 13). I know that CPU usually raises an exception when there is a mismatch of privilege levels.
But who maps the user/supervisor mode bit to the privilege level, is it the MMU or the CPU?
Particularly, I am not able to interpret who would raise an exception when I clear the _PAGE_USER flag of the pte entry of a page, I expect a fault to be raised by the MMU (or is it the processor?)
Please point me to the resources if you can so that I can read up in case this is available somewhere. Thanks !
But who maps the user/supervisor mode bit to the privilege level, is it the MMU or the CPU?
From (https://software.intel.com/sites/default/files/319433-014.pdf)
Every access to a linear address is either a supervisor-mode access or a user-mode access. All accesses performed while the current privilege level (CPL) is less than 3 are supervisor-mode accesses. If CPL = 3, accesses are generally user-mode accesses.
To be short, ring 3 is user, rings 0-2 are supervisor.
Particularly, I am not able to interpret who would raise an exception when I clear the _PAGE_USER flag of the pte entry of a page, I expect a fault to be raised by the MMU (or is it the processor?)
Fault is raised by the MMU which is a part of the CPU on modern computers. So, that doesn't really matter.
Linux Kernel Development by Robert Love and Understanding the Linux Kernel by Daniel P. Bovet excellently cover this topic. Former has less details about linux kernel implementation on x86 and generally is easier to understand.