I have a pakcgae in which I declare a bunch of subtypes and types. In Active HDL, there seems to be a problem whenever I try to make a port out of a subtype, so I'm wondering if there is a way to convert them to types instead. The following would be a subtype i'd like to convert:
subtype word_t is std_logic_vector(15 downto 0); -- Word (definition)
Is this possible without just creating a type that is a record, or an array? thanks
Don't think it is possible to directly create a type
based on another subtype
, but without the subtype
it can be done like:
type word_t is array (15 downto 0) of std_logic;
However, creating a new type
for the port will make use of the port cumbersome, due to the hard-type nature of VHDL.
An alternative work-around may be to make a subtype
with the range for word_t
, like:
subtype word_range_t is natural range 15 downto 0;
and then use that subtype
with std_logic_vector
in the port
declaration, like:
... std_logic_vector(word_range_t);
The port is then still compatible with std_logic_vector
, and the size of the word is then still easily maintainable.