Error: Unknown formal identifier on Vhdl Testbench

Question

When compiling my testbench I get the following error:

"Unknown formal identifier "_"". This happens for every input of the entity I'm testing.

Here is my code:

entity Scoreboard is
    port( BTN: in std_logic_vector(3 downto 0);
        SWITCHES: in std_logic_vector(17 downto 0);
        CLK_50 : in std_logic;
        maxreset: in std_logic;
        Display0: out std_logic_vector(6 downto 0);
        Display1: out std_logic_vector(6 downto 0);
        Display2: out std_logic_vector(6 downto 0);
        Display3: out std_logic_vector(6 downto 0);
        Display4: out std_logic_vector(6 downto 0);
        Display5: out std_logic_vector(6 downto 0);
        Display6: out std_logic_vector(6 downto 0);
        Display7: out std_logic_vector(6 downto 0);
        GREEN: out std_logic_vector(7 downto 0);
        RED: out std_logic_vector(17 downto 0));        

end Scoreboard;

And my test bench:

entity Scoreboard is
end Scoreboard;

architecture Stimulus of Scoreboard is
-- Sinais para ligar as entradas da uut
signal s_BTN: std_logic_vector(3 downto 0);
signal s_SWITCHES: std_logic_vector(17 downto 0);
signal s_CLK_50, s_maxreset: std_logic;

-- Sinal para ligar as saidas da uut
signal s_Display0, s_Display1, s_Display2, s_Display3, s_Display4, s_Display5, s_Display6, s_Display7: std_logic_vector(6 downto 0);
signal s_GREEN: std_logic_vector(7 downto 0);
signal s_RED: std_logic_vector(17 downto 0);


-- Outros 
-- Outros
constant clk_period: time := 20 ns; -- 50MHz

begin
-- Instanciação da UUT --

uut:  entity work.Scoreboard(Shell)
        port map(BTN => s_BTN,
                    SWITCHES => s_SWITCHES,
                    CLK_50 => s_CLK_50,
                    maxreset => s_maxreset,
                    Display0 => s_Display0,
                    Display1 => s_Display1,
                    Display2 => s_Display2,
                    Display3 => s_Display3,
                    Display4 => s_Display4,
                    Display5 => s_Display5,
                    Display6 => s_Display6,
                    Display7 => s_Display7,
                    GREEN => s_GREEN,
                    RED => s_RED);

The entity "Scoreboard" is not the top level entity but has many entities under it.

Answer 1

You have two entities with the name Scoreboard. The second one you refer to as your test bench has no port interface list. As soon as the entity declaration:

entity Scoreboard is
end Scoreboard;

is analyzed you no longer have a port interface declaration to reference in a direct entity instantiation statement.

Change the name of your test bench entity (e.g. Scoreboard_tb). Also in the architecture declaration.