I'm using Quartus II and i need to create a 256 x 4B (1KB) memory out of 8 components of 128x1B, but i'm a begginer in vhdl.
Here's the 128x1B component(this is not where the problem lies), created using MegaWizard Quartus II plugin:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY RAM_128B_MegaWizard IS
PORT
(
address : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
clock : IN STD_LOGIC := '1';
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END RAM_128B_MegaWizard;
ARCHITECTURE SYN OF ram_128b_megawizard IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
power_up_uninitialized : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
wren_a : IN STD_LOGIC ;
clock0 : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(7 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
intended_device_family => "Cyclone II",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 128,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "UNREGISTERED",
power_up_uninitialized => "FALSE",
widthad_a => 7,
width_a => 8,
width_byteena_a => 1
)
PORT MAP (
wren_a => wren,
clock0 => clock,
address_a => address,
data_a => data,
q_a => sub_wire0
);
END SYN;
Now here's the problem. I'm trying to use port map to instantiate the memory components and i'm getting the following errors
Error (10500): VHDL syntax error at RAM_256x4B.vhd(50) near text "1.1"; expecting "end", or "(", or an identifier, or a concurrent statement
Error (10500): VHDL syntax error at RAM_256x4B.vhd(51) near text ";"; expecting "<="
Error (10500): VHDL syntax error at RAM_256x4B.vhd(53) near text ";"; expecting "<="
Error (10500): VHDL syntax error at RAM_256x4B.vhd(55) near text ";"; expecting "<="
Error (10500): VHDL syntax error at RAM_256x4B.vhd(57) near text ";"; expecting "<="
Error (10500): VHDL syntax error at RAM_256x4B.vhd(60) near text ";"; expecting "<="
Error (10500): VHDL syntax error at RAM_256x4B.vhd(62) near text ";"; expecting "<="
Error (10500): VHDL syntax error at RAM_256x4B.vhd(64) near text ";"; expecting "<="
Error (10500): VHDL syntax error at RAM_256x4B.vhd(66) near text ";"; expecting "<="
Here's the code. My address have to be of size 10 bits and i'm using a decoder and a mux through packages.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.RAM_128B_MegaWizard_package.all;
use work.dec1to2_package.all;
use work.mux2to1_package.all;
entity RAM_256x4B is
generic(
depth : integer range 1 to 10 := 10;
width: integer range 1 to 32 := 32;
init_file : string := "init_file2.mif");
-- .mif filename
port(Clock : in std_logic;
WrEn: in std_logic;
-- write control signal
Address : in std_logic_vector(depth-1 downto 0);
-- read and write addresses
data : in std_logic_vector(width-1 downto 0);
-- data to be written
DataOut : out std_logic_vector(width-1 downto 0));
-- memory read output
end RAM_256x4B;
architecture behavior of RAM_256x4B is
signal dOut0: std_logic_vector(width-1 downto 0);
signal dOut1: std_logic_vector(width-1 downto 0);
signal En: std_logic_vector(0 to 1);
begin
decoder: dec1to2 port map (Address(depth-3), WrEn, En);
1.1: RAM_128B_MegaWizard port map
(Clock, En(0), Address(depth-4 downto 0), data(width-1 downto 24), dOut0(width-1 downto 24));
1.2: RAM_128B_MegaWizard port map
(Clock, En(0), Address(depth-4 downto 0), data(23 downto 16), dOut0(23 downto 16));
1.3: RAM_128B_MegaWizard port map
(Clock, En(0), Address(depth-4 downto 0), data(15 downto 8), dOut0(15 downto 8));
1.4: RAM_128B_MegaWizard port map
(Clock, En(0), Address(depth-4 downto 0), data(7 downto 0), dOut0(7 downto 0));
2.1: RAM_128B_MegaWizard port map
(Clock, En(1), Address(depth-4 downto 0), data(width-1 downto 24), dOut1(width-1 downto 24));
2.2: RAM_128B_MegaWizard port map
(Clock, En(1), Address(depth-4 downto 0), data(23 downto 16), dOut1(23 downto 16));
2.3: RAM_128B_MegaWizard port map
(Clock, En(1), Address(depth-4 downto 0), data(15 downto 8), dOut1(15 downto 8));
2.4: RAM_128B_MegaWizard port map
(Clock, En(1), Address(depth-4 downto 0), data(7 downto 0), dOut1(7 downto 0));
mux: mux2to1 port map (dOut0, dOut1, Address(depth-3),DataOut);
end behavior;
I know it's incomplete, but whatever i do compilation gives me the same errors. Even if the part after begin and end architecture is just
1.1: RAM_128B_MegaWizard port map
(Clock, En(0), Address(depth-4 downto 0), data(width-1 downto 24), dOut0(width-1 downto 24));
the same will happen.
I understand port map can't be used inside a process, but a component with process(the 128x1B) also can't be port mapped? How can i combine these components to make what i want?
It looks to me like you're having a problem doing your port mapping by reference. Here's the component you're instantiating:
address : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
clock : IN STD_LOGIC := '1';
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
So if you're doing by reference, you should have this instantiation:
inst_1_1 : RAM_128B_MegaWizard port map
(Address(depth-4 downto 0), Clock, data(width-1 downto 24), En(0), dOut0(width-1 downto 24));
Notice the placement of the signals. This is why I prefer to do explicit port mapping, you'll make less mistakes.
Also I'm not sure what restrictions there are against your instantiation name, but 1.1 doesn't seem like a good name to me. Try something that begins with a letter and only has underscores, not periods.