delayed attribute in VHDL

Question

I'm trying to create a delayed version ('s_dlyd') of a signal ('s') using the 'delayed attribute in VHDL.

My code (below) compiles and simulates (using Xilinx webpack, ISIM) and 's' undergoes the expected '0/1' transitions.

s_dlyd simply sits at '1' however (i.e. it isn't a 5ns-delayed copy of 's' I'd (naively?!) expected.

I'm guessing I'm missing something fundamental about the way VHDL schedules transitions. I've tried numerous of variations of the code (splitting the line "s<=..." into 3; trying things like "s_dlyd <= s'delayed(5 ns) after 11 ns" etc.) but none give me a delayed copy of s.

Any help appreciated. Thankyou

    architecture Behavioral of five_three is
      signal s : STD_LOGIC := '1';
      signal s_dlyd: STD_LOGIC;
    begin
      my_process :  process is
    begin
    s <= '1', '0' after 10 ns, '1' after 20 ns;
    s_dlyd <= s'delayed(5 ns);
    wait for 50 ns;
    s <= '0' ;
    wait;
    end process;
    end architecture;

Answer 1

I expect s_dlyd to be '1' after 5 ns, previously 'U'.

A signal equivalent to signal S delayed T units of time. The value of S'DELAYED(t) at time Tn is always equal to the value of S at time Tn-t.

The current effective value of s will be assigned to s_dyld after 5 ns in this case. The current value of s (Now = 0 ns) is the default value ('1').

Your process is only going to get invoked once because of the wait statements (the last one wait ;).

The equivalent sequential signal assignment statement is

 s_dyld <= transport s after 5 ns;

You can assign s_dyld in a separate process sensitive to s or as a concurrent signal assignment statement or restructure your current wait statement with more waits and more s_dyld assignments.