The machine code for the JMP instruction comprises of:
opcode - 11CCC010 (where CCC is the state of the flag bit used to set the condition) 8 bits and
address for the jump - let's say a 16 bit address.
First there is a fetch operation of the opcode so it needs 1 machine cycle. The state of the flag bit is checked. If condition satisfies then the address is read else it is not. Checking whether the condition satisfies should not take any significant clock cycles since it is determined from the state of the flag bits.
i - Now if condition satisfies: no. of machine cycles needed = 1 (for fetch) + 2 (for reading the address which is 16 bits) = 3
ii. if condition doesn't satisfy: there should be no read cycles (after the fetch cycle) and so the number of machine cycles needed must be 1 ie the fetch cycle only.
But the material I am refering to to learn microprocessors says it will need 2 machine cycles but doesn't tell why and hence my confusion. Should it be 1 machine cycle or 2 machine cycles?
In case there is some confusion over machine cycle and clock cycle, please feel free to answer in any.
Although its counterintuitive to those of us used to the 8080 or z80, checking this documentation confirms your belief. JC takes two machine cycles and seven clock cycles if the condition isn't met but it takes three machine cycles and ten clock cycles if it is. Compare and contrast with the z80 where it's always three machine cycles and ten clock cycles, whether taken or not.
However, I think your confusion is because you imagine that not reading the address is somehow free but there's still the PC to increment.
Both branches of the processor family have a baseline two-cycle cost. That'll account for decoding and making the decision and, because they're pipelined, the read of the first byte of the target address will have begun elsewhere.
At that point I'd imagine the 8085 is smart enough that if the branch isn't going to be taken it can decline to read the second byte of the the target address and just increment the PC again. The 8080 and z80 have probably allowed the second byte read to begin, and quite probably can't increment the PC without reading from it in general, so they follow through on that and then discard the entire target address.
So, in short: it doesn't wait for a decision to start reading the target address; once the read of the low byte is in progress it lets that finish. The alternatives would have been an instruction that takes longer if the branch is taken, and the need to be able to do a double increment without read of the PC, which probably doesn't otherwise come up.
All speculation, of course. Does anybody have an actual 8085 and a logic analyser? They could check whether a first access cycle occurs even if the jump isn't taken.