VDHL: when else clause inside case clause

Question

I need to implement a slt instruction from the MIPS32.

The operation itself is simple. The output is 1 if the input_1 is smaller then the input_2 else is 0.

From the MIPS Specification:

if GPR[rs] < GPR[rt] then
GPR[rd] ← 0(GPRLEN-1) || 1
else
GPR[rd] ← 0(GPRLEN)
endif

Because i decode the funct in my alu-stage i can directly perform the computation. So far so good, but i dont understand, why vcom does only accept the first option. The second option always produce a "Illegal sequential statement.".

The second question is, if the equation is true, does the output has to be "0...01" or rather "111..111"?

case funct is
*
*
*
--first option
when "101010" => if (signed(s_alu_input_1) < signed(s_alu_input_2)) then
                s_alu_result(0) <= '1';
                s_alu_result(31 downto 1) <= (others => '0');
                else 
                    s_alu_result <= (others => '0');
                end if;
--second option
when "101010" => s_alu_result(0) <= '1' when signed(s_alu_input_1) < signed(s_alu_input_2) else
                                '0';
                 s_alu_result(31 downto 1) <= (others => '0');
*
*
*
end case;

Answer 1

In VHDL, you are not allowed to use the when statement in a process. You need to be using if.

This line:

s_alu_result(0) <= '1' when signed(s_alu_input_1) < signed(s_alu_input_2) else
                            '0';

when in VHDL can only be used in combinational assignments outside of a process.