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wait on an untimed signal in VHDL testbench


I have written a simulation process that sets or changes signals sequentially as required, I use wait statements normally to wait certain time intervals or wait on signal assignments, but that is true only when I know when a signal should be coming, an example:

    reset      <= '1';
    write      <= '0';
    read       <= '0';
    wait for 25 ns;
    reset      <= '0';
    chipselect <= '1';
    wait until clk = '1';

but now I need to do something different, I have a signal that is normally 0, and I need to pause simulation stimulus whenever it is turned to 1. the signal however is not timed. meaning I cannot do it with a simple wait statement because the simulation will wait for it only at a certain time. I want that effect to happen at all times. how to do something like this?


Solution

  • Based on the description, I understand that you want to pause stimuli generation based on a signal, so stimuli time is extended corresponding to the time of the pause.

    For this a signal with the active time (named active_time below) can be created, and stimuli can then be generated based on this time. The active time is only running when the active_stimuli is TRUE.

    A support procedure (named active_wait_for below) corresponding to wait for can then be created to wait for the requested amount of active time, for use in the stimuli generation process.

    Suggestion for code:

    architecture syn of tb is
    
      -- Active declarations
      signal   active_stimuli    : boolean := TRUE;
      constant ACTIVE_RESOLUTION : time := 1 ps;
      signal   active_time       : time := 0 ps;
    
      -- Wait procedure for active delay
      procedure active_wait_for(delay : time) is
        variable active_time_start_v : time;
      begin
        active_time_start_v := active_time;
        if delay > 0 ps then
          wait until active_time >= active_time_start_v + delay;
        end if;
      end procedure;
    
      -- Stimuli signal
      signal stimuli_a : std_logic;
      signal stimuli_b : std_logic;
    
    begin
    
      -- Active time generation
      process is
      begin
        wait for ACTIVE_RESOLUTION;
        if active_stimuli then
          active_time <= active_time + ACTIVE_RESOLUTION;
        else  -- Save execution time in loop by wait until
          wait until active_stimuli;
        end if;
      end process;
    
      -- Stimuli generation
      process is
      begin
        stimuli_a <= '0';
        stimuli_b <= '0';
        wait until active_time >= 2 ns;
        stimuli_a <= '1';
        active_wait_for(3 ns);
        stimuli_b <= '1';
        wait;
      end process;
    ...
    

    Waveform showing operation is below:

    enter image description here

    Note that polarity is different than the signal in the question, but naming was clearer with this polarity.