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makefilealiastargetsynonym

Alias target name in Makefile

The Problem:

Is it possible to give a target a different name or alias, such that it can be invoked using either the original target name or the alias.

For example something like

/very/long/path/my_binary: dep_a dep_b dep_c
    # Compile

# Desired command
ALIAS my_binary = /very/long/path/my_binary

# NOTE: Notice the use of 'my_binary' in the dependencies
data1: my_binary datafile
    # Build data file using compiled my_binary

Attempt 1: .PHONY

I have tried using a .PHONY target:

.PHONY: my_binary
my_binary: /very/long/path/my_binary

This works great when invoked from the command-line:

# Runs rule 'my_binary' and then *only* runs rule '/very/long/path/my_binary'
# if the rule '/very/long/path/my_binary' needs updating.
make my_binary

However, this does not work well when the alias my_binary is listed as a dependency:

# *Always* thinks that rule 'data1' needs updating, because it always thinks that
# the .PHONY target 'my_binary' "needs updating". As a result, 'data1' is
# rebuilt every time.
make /very/long/path/my_binary

Possible hack?

A possible hack is to use an empty target as suggested in an answer to this question, but that would require introducing fake files with names corresponding to the alias:

my_binary: /very/long/path/my_binary
    touch my_binary

This will clutter the main directory with files! Placing the fake files in a sub-directory would defeat the purpose, as the alias would have to be referred to as 'directory/my_binary'

Solution

  • I don't think there's any way to do it so that you can use the alias from within your makefile as well as the command line, except by creating those temporary files.

    Why can't you just set a variable in the makefile, like:

    my_binary = /very/long/path/my_binary

    then use $(my_binary) everywhere in the makefile? I don't see any point in creating a real alias target for use inside the makefile.