VHDL: Is there a convenient way to assign ascii values to std_logic_vector?

In verilog, I can assign a string to a vector like:
```
wire [39:0] hello;
assign hello = "hello"; 
```

In VHDL, I'm having difficulty finding a method like this:

SIGNAL hello : OUT std_logic_vector (39 DOWNTO 0);
...
hello <= "hello";

I've been using:

hello <= X"65_68_6c_6c_6f";

which is unclear and time consuming for large strings.

I've looked at the textio package and thetxt_util package, but neither seem to be very clear on how to interpret a string and convert it to std_logic.

Is there a simple method of assigning ascii codes to std_logic in VHDL?

Here's a minimal example:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY test IS
PORT(
   ctrl : IN std_logic;
   stdout : OUT std_logic_vector (39 DOWNTO 0)
);
END ENTITY;

ARCHITECTURE rtl OF test IS
   SIGNAL temp : std_logic_vector (39 DOWNTO 0);
BEGIN
   stdout <= temp;
   PROCESS(ctrl)
   BEGIN
      IF (ctrl = '0') THEN
         temp <= "hello"; -- X"68_65_6C_6C_6F";
      ELSE
         temp <= "world";
      END IF;
   END PROCESS;

END rtl;

Solution

This one varies little for Morten's answer - it only uses one multiply, it copies the string instead of creating an alias, it uses an additional variable and it returns a standard logic vector with an ascending index range.

From a package called string_utils:

library ieee; 
use ieee.numeric_std.all;
-- ...
    function to_slv(s: string) return std_logic_vector is 
        constant ss: string(1 to s'length) := s; 
        variable answer: std_logic_vector(1 to 8 * s'length); 
        variable p: integer; 
        variable c: integer; 
    begin 
        for i in ss'range loop
            p := 8 * i;
            c := character'pos(ss(i));
            answer(p - 7 to p) := std_logic_vector(to_unsigned(c,8)); 
        end loop; 
        return answer; 
    end function;

You could add an argument with a default specifying ascending/descending index range for the return value. You'd only need to provided the argument for the non default.