Connect internal signal to output port in MyHDL module

Question

Considering the following example (a simple 8-bit counter), is there a simpler way to connect the internal s_count signal to the o_count port?

def counter(i_clk, i_reset, o_count):

    """ A free-running 8-bit counter with a synchronous reset """

    s_count = Signal(intbv(0)[8:])

    @always(i_clk.posedge)
    def count():
        if i_reset == 1:
            s_count.next = 0
        else:        
            s_count.next = s_count + 1

    @always_comb
    def outputs():
        o_count.next = s_count        

    return count, outputs

Of course, I could directly increment o_count in the count function but this translates to an inout port in the generated VHDL module, which I don't want.

Answer 1

I suspect directly incrementing o_count is an acceptable solution.

Indeed, it translates to an inout because you cannot read output ports in VHDL.

However, this will only happen when you convert this module as a top module. It is likely that this is a small submodule however. In that case, the hierarchy is flattened out and o_count will be an internal signal.