I am writing a simple MIPS architecture (supports only R-type and lw/sw instructions) in VHDL.
I am currently clocking each of the pipeline register on the rising edge. However, I had trouble deciding whether to clock register file, data memory and program counter on the rising edge or the falling edge.
After looking up online, it's pretty unanimous that you write to a register file on the falling edge. However, it's not so unanimous when it comes to data memory: some say to trigger the write to data memory on rising edge and some say falling edge, so I am a little bit confused here and need some explanation.
Oh, I also mentioned program counter because 1 website said to used falling edge; that kind of confused too as to why PC has to be clocked at the falling edge. That 1 website is this if anyone is interested: https://ls12-www.cs.tu-dortmund.de/daes/en/lehre/downloads/ravi/documentation/pipeline.html
Thanks very much.
Read request of value written in same cycle occurs in all kind of designs, and is usually handled with bypass logic, whereby the written value is forwarded directly to the read output, without going through the registers. Such bypass is done in a single clock design.
Whether design with both rising and falling edge is to prefer (faster/better) in an FPGA, depends on the specific timing of the control signals and clocks. However, in FPGA all flip-flops are usually rising edge type, so the falling edge is made through a separate clock network that provides the inverted clock. The worst case skew calculated in Static Timing Analysis (STA) between these two clock networks may be so large, that there is no timing advantage in the introduction of a falling edge clock instead of just doing the bypass the usual way.
For implementation in an ASIC, there may be an advantage in a dual edge design, for example if the clock networks can be implemented with small skew, or if falling edge flip-flops are available in the target technology.