VHDL: Unable to read output status

Question

I'm attempting to compile in ModelSim 10.0 and I receive a compile error stating: 'Cannot read output status'.

Here's a snippet of the code. It'd be brilliant if someone could tell me what I'm doing wrong.

entity controller_entity is
generic( entryCount : positive := 2;
         ....);
port(
    clk         : in  std_logic;
    ....
    entry_car_entered : out std_logic_vector(0 to entryCount-1)
);
end entity controller_entity;

architecture controller_v1 of controller_entity is
signal cars_entered : std_logic_vector(0 to entryCount-1);

component entry is
    port(
        clk       : in  std_logic;
        ....
        car_passed: out std_logic  --Output to higher level
    );
end component;

begin   
    CREATE_ENTRANCES: for i in 0 to entryCount-1 generate
                entryi : entry port map(clk => clk,
                        ....
                car_passed => entry_car_entered(i) -- This line causes the problem.                                             

                        end generate CREATE_ENTRANCES;

    .....

);
end architecture controller_v1;

I think I can fix this if I switch to compiling with VHDL 2008 but I'm trying to stick with 1993. Any advice on this issue would be deeply appreciated.

Answer 1

VHDL-2008 allows read of a port in out mode, but previous VHDL versions do not, so based on the error message 'Cannot read output status', and your comment about fixing the problem through use of VHDL-2008, it sounds like this is the problem.

However, the error message may actually be 'Cannot read output "status"', where "status" is a reference to an output named "status" elsewhere in undisclosed code. You may want to search for "status" in all code, to see if a "status" port with mode out is referenced for read.

If so, the problem can be fixed in VHDL-2002 if an internal signal is driven by the component, and the internal signal then drives the out port. This internal signal may then be read internally.