I have following simple testcase :
library ieee;
use ieee.std_logic_1164.all;
entity top is
end top;
architecture top of top is
component foo
port (A : std_logic_vector(1 downto 0));
end component;
begin
inst : foo port map (A(1) => '0', A(0) => '0');
end top;
------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity foo is
port (A : std_logic_vector(1 downto 0));
end foo;
architecture foo of foo is
begin
end foo;
When running modelsim on this, it runs fine. But, when I run modelsim with option '-87', it gives me error that Error: top.vhd(13): (vcom-1451) Actual (enumeration literal '0') for formal "A" is not signal name. I am not getting this. Is this some illegal RTL in VHDL'87?
If this is not supported in VHDL'87, then what would be right way to connect a constant to instance pin.
Looking in Modelsim's Verror messages:
vcom Message # 1451: The actual designator is not a static signal name, it is an expression. In a VHDL 1987 port map, the actual designator in an association element must be either a static signal name or a conversion function call whose only argument is a static signal name. In a subprogram association list in any VHDL language version, the actual associated with a class SIGNAL subprogram parameter must be a static signal name.
Later versions of VHDL allow flexibility in the actual in a port map.
Try using the -93, -2002, or -2008 switch to vcom.
[DOC: IEEE Std 1076-1987 VHDL LRM - 2.1.1.2 Signal parameters,
4.3.3.2 Association Lists]
[DOC: IEEE Std 1076-1993 VHDL LRM - 2.1.1.2 Signal parameters]
So, yes there's a difference in what is valid for an an actual in a port association. The -1993 'liberalization' would also be applicable on later versions (-2002, -2008).
The actual needs to be named and not simply an expression. Inputs with default values can be left open.