Given an array type:
type enc is array (integer 0 to 1) of std_logic_vector(3 downto 0);
Is it possible to access attributes of the array subtype (The std_logic_vector)?
I would have thought that something like this was possible:
enc(0)'range -> 3 downto 0 (Taking the range of element number 0)
This is an error in my simulator.
Looking at the LRM(14.1) there is a range attribute for array elements:
A'RANGE [(N)]
This attribute seems to be only able to return the range of the array's dimensions, i.e the "0 to 10", and not the subtype.
One solution could be to make a constant of that type:
constant tmp : enc :=(
0 => "0000",
1 => "0001"
)
And take the range of that constant:
tmp(0)'range
This works, however i feel it should be possible using the type alone, since it is fully constrained.
Your problem is that you try to use an attribute on a type. However, range is only defined for arrays (hence A in the prototype).
This means, you will need to use an actual array, even though your array type is constrained.
-- Declarations
-- Constrained Array Type
type enc is array (integer 0 to 1) of std_logic_vector(3 downto 0);
-- Unconstrained Array Type (pre-VHDL 2008)
type enc_alt is array (integer range <>) of std_logic_vector(3 downto 0);
-- Unconstrained Array Type with Unconstrained Element Type (VHDL 2008)
type enc2008 is array (integer range <>) of std_logic_vector;
subtype enc2008_sub is enc2008(open)(3 downto 0);
signal test0 : enc;
signal test1 : enc_alt(0 to 1);
signal test2 : enc2008(0 to 1)(3 downto 0);
-- Array Attributes (VHDL 2002 and prior)
test0(0)'range -- get element 0 and check its range
test1(0)'range
test2(0)'range
-- Array Attributes (VHDL 2008 only)
test0'element'range -- get element type and check its range
test1'element'range
test2'element'range
-- Type Attributes (VHDL 2008 only)
enc'element'range
enc_alt'element'range
enc2008'element'range
enc2008_sub'element'range
You will have to check with your simulator and with your synthesis tool whether they support the VHDL 2008 attribute 'element and unconstrained array element types.
Xilinx ISE does not support VHDL-2008 that great and Modelsim only recently started in 10.1a, I believe. Alterra is said to have good support for VHDL-2008 in their Quartus Suite, though I have not recently worked with it.