How to instanciate a component for generation multiple component parallel?

Question

I try to generate a multiple componnt by using the generic map , but i dont know if my code VHDL is correct or no ? here the programm generate 5 parallel component ( comp) for forming bascule

            entity bascule is
             Port ( X1,X2,X3,X4,X5: in  STD_LOGIC;
                      Y1,Y2, Y3,Y4,Y5 : in  STD_LOGIC;
                      Z1,Z2,Z3,Z4,Z5 : in  STD_LOGIC;
                      S1,S2,S3,S4,S5 : out  STD_LOGIC);
        end bascule;

        architecture Behavioral of bascule is
        component comp
        Generic( N: integer :=1);
        Port ( X : in  STD_LOGIC;
                      Y : in  STD_LOGIC;
                      Z: in  STD_LOGIC;
                      S : out  STD_LOGIC);
        end component;

        begin
        m1 : comp generic map (5)
                     port map ( X1,Y1,Z1, S1);
         m2 : comp generic map (5)
                     port map ( X2,Y2,Z2, S2);
        m3 : comp generic map (5)
                     port map ( X3,Y3,Z3, S3);
        m4 : comp generic map (5)
                     port map ( X4,Y4,Z4, S4);
        m5 : comp generic map (5)
                     port map ( X5,Y5,Z5, S5);

        end Behavioral;

i want to know the way to generate any number of component ?

my best regards

Answer 1

library ieee;
use ieee.std_logic_1164.all;

-- dummy comp this analyzes and elaborates

entity comp is
    Generic( N: integer :=1);
    Port ( 
        X: in   STD_LOGIC;
        Y: in   STD_LOGIC;
        Z: in   STD_LOGIC;
        S: out  STD_LOGIC
    );
end entity;


architecture behave of comp is

begin
    S <= X and Y and Z;
end architecture;

library ieee;
use ieee.std_logic_1164.all;

entity bascule is
    Port ( 
        -- X1,X2,X3,X4,X5:  in  STD_LOGIC;
        -- Y1,Y2, Y3,Y4,Y5: in  STD_LOGIC;
        -- Z1,Z2,Z3,Z4,Z5:  in  STD_LOGIC;
        -- S1,S2,S3,S4,S5:  out STD_LOGIC

-- and yes, you could pass the number of elements in these as a generic:

        X:      in   std_logic_vector (1 to 5);
        Y:      in   std_logic_vector (1 to 5);
        Z:      in   std_logic_vector (1 to 5);
        S:      out  std_logic_vector (1 to 5)
    );
end bascule;

architecture Behavioral of bascule is
component comp
    Generic( N: integer :=1);
    Port ( 
        X: in  STD_LOGIC;
        Y: in  STD_LOGIC;
        Z: in  STD_LOGIC;
        S: out  STD_LOGIC
    );
end component;

begin
M_gen:

-- and use the same generic as above in the generate iteration scheme:

    for i in 1 to 5 generate
M:
        comp generic map (5) 
            port map (
                X(i), Y(i), Z(i), S(i)
                );
    end generate;

-- m1 : comp generic map (5)
--              port map ( X1,Y1,Z1, S1);
--  m2 : comp generic map (5)
--              port map ( X2,Y2,Z2, S2);
-- m3 : comp generic map (5)
--              port map ( X3,Y3,Z3, S3);
-- m4 : comp generic map (5)
--              port map ( X4,Y4,Z4, S4);
-- m5 : comp generic map (5)
--              port map ( X5,Y5,Z5, S5);

end Behavioral;

Using a generic to control a generate statement interation instantiating comp

Because you appear confused about how to use generics to control the number of components, I'll demonstrate:

library ieee;
use ieee.std_logic_1164.all;

-- dummy comp
entity comp is
    Port ( 
        X: in   STD_LOGIC;
        Y: in   STD_LOGIC;
        Z: in   STD_LOGIC;
        S: out  STD_LOGIC
    );
end entity;

architecture behave of comp is

begin
    S <= X and Y and Z;
end architecture;

library ieee;
use ieee.std_logic_1164.all;

entity bascule is
    generic (MSIZE:  natural := 1);
    Port ( 
        X:      in   std_logic_vector (1 to MSIZE);
        Y:      in   std_logic_vector (1 to MSIZE);
        Z:      in   std_logic_vector (1 to MSIZE);
        S:      out  std_logic_vector (1 to MSIZE)
    );
end bascule;

architecture Behavioral of bascule is

component comp
    Port ( 
        X: in   STD_LOGIC;
        Y: in   STD_LOGIC;
        Z: in   STD_LOGIC;
        S: out  STD_LOGIC
    );
end component;

begin
Mgen:
    for i in 1 to MSIZE generate
M:
        comp 
            port map (
                X(i), Y(i), Z(i), S(i)
            );
    end generate;

end Behavioral;

library ieee;
use ieee.std_logic_1164.all;

entity bascule_tb is
end entity;

architecture foo of bascule_tb is

    constant MSIZE:     natural :=5;
     signal X:          std_logic_vector (1 to MSIZE);
     signal Y:          std_logic_vector (1 to MSIZE);
     signal Z:          std_logic_vector (1 to MSIZE);
     signal S:          std_logic_vector (1 to MSIZE);

begin

DUT: entity work.bascule
    generic map (MSIZE)
    port map (
        X => X,
        Y => Y,
        Z => Z,
        S => S 
    );

end architecture;

We get MSIZE number of comp components based on the generic MSIZE, which is passed the constant MSIZE where bascule is instantiated in the test bench bascule_tb. This analyzes, elaborates and runs (though it doesn't actually do anything).